ENC28j60/Debug/STM32F030_ENC28J60.list

STM32F030_ENC28J60.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   000000c0  08000000  08000000  00010000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         000019cc  080000c0  080000c0  000100c0  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000038  08001a8c  08001a8c  00011a8c  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM.extab    00000000  08001ac4  08001ac4  00020010  2**0
                  CONTENTS
  4 .ARM          00000000  08001ac4  08001ac4  00020010  2**0
                  CONTENTS
  5 .preinit_array 00000000  08001ac4  08001ac4  00020010  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  6 .init_array   00000004  08001ac4  08001ac4  00011ac4  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  7 .fini_array   00000004  08001ac8  08001ac8  00011ac8  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  8 .data         00000010  20000000  08001acc  00020000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  9 .bss          000000d4  20000010  08001adc  00020010  2**2
                  ALLOC
 10 ._user_heap_stack 00000604  200000e4  08001adc  000200e4  2**0
                  ALLOC
 11 .ARM.attributes 00000028  00000000  00000000  00020010  2**0
                  CONTENTS, READONLY
 12 .debug_info   0000c890  00000000  00000000  00020038  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 13 .debug_abbrev 00001d0c  00000000  00000000  0002c8c8  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 14 .debug_loc    0000a99f  00000000  00000000  0002e5d4  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 15 .debug_aranges 00000ac8  00000000  00000000  00038f78  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 16 .debug_ranges 00000a48  00000000  00000000  00039a40  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 17 .debug_macro  00002ad1  00000000  00000000  0003a488  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 18 .debug_line   000108df  00000000  00000000  0003cf59  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 19 .debug_str    0005e418  00000000  00000000  0004d838  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 20 .comment      00000050  00000000  00000000  000abc50  2**0
                  CONTENTS, READONLY
 21 .debug_frame  00001c24  00000000  00000000  000abca0  2**2
                  CONTENTS, READONLY, DEBUGGING, OCTETS

Disassembly of section .text:

080000c0 <__do_global_dtors_aux>:
 80000c0:	b510      	push	{r4, lr}
 80000c2:	4c06      	ldr	r4, [pc, #24]	; (80000dc <__do_global_dtors_aux+0x1c>)
 80000c4:	7823      	ldrb	r3, [r4, #0]
 80000c6:	2b00      	cmp	r3, #0
 80000c8:	d107      	bne.n	80000da <__do_global_dtors_aux+0x1a>
 80000ca:	4b05      	ldr	r3, [pc, #20]	; (80000e0 <__do_global_dtors_aux+0x20>)
 80000cc:	2b00      	cmp	r3, #0
 80000ce:	d002      	beq.n	80000d6 <__do_global_dtors_aux+0x16>
 80000d0:	4804      	ldr	r0, [pc, #16]	; (80000e4 <__do_global_dtors_aux+0x24>)
 80000d2:	e000      	b.n	80000d6 <__do_global_dtors_aux+0x16>
 80000d4:	bf00      	nop
 80000d6:	2301      	movs	r3, #1
 80000d8:	7023      	strb	r3, [r4, #0]
 80000da:	bd10      	pop	{r4, pc}
 80000dc:	20000010 	.word	0x20000010
 80000e0:	00000000 	.word	0x00000000
 80000e4:	08001a74 	.word	0x08001a74

080000e8 <frame_dummy>:
 80000e8:	4b04      	ldr	r3, [pc, #16]	; (80000fc <frame_dummy+0x14>)
 80000ea:	b510      	push	{r4, lr}
 80000ec:	2b00      	cmp	r3, #0
 80000ee:	d003      	beq.n	80000f8 <frame_dummy+0x10>
 80000f0:	4903      	ldr	r1, [pc, #12]	; (8000100 <frame_dummy+0x18>)
 80000f2:	4804      	ldr	r0, [pc, #16]	; (8000104 <frame_dummy+0x1c>)
 80000f4:	e000      	b.n	80000f8 <frame_dummy+0x10>
 80000f6:	bf00      	nop
 80000f8:	bd10      	pop	{r4, pc}
 80000fa:	46c0      	nop			; (mov r8, r8)
 80000fc:	00000000 	.word	0x00000000
 8000100:	20000014 	.word	0x20000014
 8000104:	08001a74 	.word	0x08001a74

08000108 <__udivsi3>:
 8000108:	2200      	movs	r2, #0
 800010a:	0843      	lsrs	r3, r0, #1
 800010c:	428b      	cmp	r3, r1
 800010e:	d374      	bcc.n	80001fa <__udivsi3+0xf2>
 8000110:	0903      	lsrs	r3, r0, #4
 8000112:	428b      	cmp	r3, r1
 8000114:	d35f      	bcc.n	80001d6 <__udivsi3+0xce>
 8000116:	0a03      	lsrs	r3, r0, #8
 8000118:	428b      	cmp	r3, r1
 800011a:	d344      	bcc.n	80001a6 <__udivsi3+0x9e>
 800011c:	0b03      	lsrs	r3, r0, #12
 800011e:	428b      	cmp	r3, r1
 8000120:	d328      	bcc.n	8000174 <__udivsi3+0x6c>
 8000122:	0c03      	lsrs	r3, r0, #16
 8000124:	428b      	cmp	r3, r1
 8000126:	d30d      	bcc.n	8000144 <__udivsi3+0x3c>
 8000128:	22ff      	movs	r2, #255	; 0xff
 800012a:	0209      	lsls	r1, r1, #8
 800012c:	ba12      	rev	r2, r2
 800012e:	0c03      	lsrs	r3, r0, #16
 8000130:	428b      	cmp	r3, r1
 8000132:	d302      	bcc.n	800013a <__udivsi3+0x32>
 8000134:	1212      	asrs	r2, r2, #8
 8000136:	0209      	lsls	r1, r1, #8
 8000138:	d065      	beq.n	8000206 <__udivsi3+0xfe>
 800013a:	0b03      	lsrs	r3, r0, #12
 800013c:	428b      	cmp	r3, r1
 800013e:	d319      	bcc.n	8000174 <__udivsi3+0x6c>
 8000140:	e000      	b.n	8000144 <__udivsi3+0x3c>
 8000142:	0a09      	lsrs	r1, r1, #8
 8000144:	0bc3      	lsrs	r3, r0, #15
 8000146:	428b      	cmp	r3, r1
 8000148:	d301      	bcc.n	800014e <__udivsi3+0x46>
 800014a:	03cb      	lsls	r3, r1, #15
 800014c:	1ac0      	subs	r0, r0, r3
 800014e:	4152      	adcs	r2, r2
 8000150:	0b83      	lsrs	r3, r0, #14
 8000152:	428b      	cmp	r3, r1
 8000154:	d301      	bcc.n	800015a <__udivsi3+0x52>
 8000156:	038b      	lsls	r3, r1, #14
 8000158:	1ac0      	subs	r0, r0, r3
 800015a:	4152      	adcs	r2, r2
 800015c:	0b43      	lsrs	r3, r0, #13
 800015e:	428b      	cmp	r3, r1
 8000160:	d301      	bcc.n	8000166 <__udivsi3+0x5e>
 8000162:	034b      	lsls	r3, r1, #13
 8000164:	1ac0      	subs	r0, r0, r3
 8000166:	4152      	adcs	r2, r2
 8000168:	0b03      	lsrs	r3, r0, #12
 800016a:	428b      	cmp	r3, r1
 800016c:	d301      	bcc.n	8000172 <__udivsi3+0x6a>
 800016e:	030b      	lsls	r3, r1, #12
 8000170:	1ac0      	subs	r0, r0, r3
 8000172:	4152      	adcs	r2, r2
 8000174:	0ac3      	lsrs	r3, r0, #11
 8000176:	428b      	cmp	r3, r1
 8000178:	d301      	bcc.n	800017e <__udivsi3+0x76>
 800017a:	02cb      	lsls	r3, r1, #11
 800017c:	1ac0      	subs	r0, r0, r3
 800017e:	4152      	adcs	r2, r2
 8000180:	0a83      	lsrs	r3, r0, #10
 8000182:	428b      	cmp	r3, r1
 8000184:	d301      	bcc.n	800018a <__udivsi3+0x82>
 8000186:	028b      	lsls	r3, r1, #10
 8000188:	1ac0      	subs	r0, r0, r3
 800018a:	4152      	adcs	r2, r2
 800018c:	0a43      	lsrs	r3, r0, #9
 800018e:	428b      	cmp	r3, r1
 8000190:	d301      	bcc.n	8000196 <__udivsi3+0x8e>
 8000192:	024b      	lsls	r3, r1, #9
 8000194:	1ac0      	subs	r0, r0, r3
 8000196:	4152      	adcs	r2, r2
 8000198:	0a03      	lsrs	r3, r0, #8
 800019a:	428b      	cmp	r3, r1
 800019c:	d301      	bcc.n	80001a2 <__udivsi3+0x9a>
 800019e:	020b      	lsls	r3, r1, #8
 80001a0:	1ac0      	subs	r0, r0, r3
 80001a2:	4152      	adcs	r2, r2
 80001a4:	d2cd      	bcs.n	8000142 <__udivsi3+0x3a>
 80001a6:	09c3      	lsrs	r3, r0, #7
 80001a8:	428b      	cmp	r3, r1
 80001aa:	d301      	bcc.n	80001b0 <__udivsi3+0xa8>
 80001ac:	01cb      	lsls	r3, r1, #7
 80001ae:	1ac0      	subs	r0, r0, r3
 80001b0:	4152      	adcs	r2, r2
 80001b2:	0983      	lsrs	r3, r0, #6
 80001b4:	428b      	cmp	r3, r1
 80001b6:	d301      	bcc.n	80001bc <__udivsi3+0xb4>
 80001b8:	018b      	lsls	r3, r1, #6
 80001ba:	1ac0      	subs	r0, r0, r3
 80001bc:	4152      	adcs	r2, r2
 80001be:	0943      	lsrs	r3, r0, #5
 80001c0:	428b      	cmp	r3, r1
 80001c2:	d301      	bcc.n	80001c8 <__udivsi3+0xc0>
 80001c4:	014b      	lsls	r3, r1, #5
 80001c6:	1ac0      	subs	r0, r0, r3
 80001c8:	4152      	adcs	r2, r2
 80001ca:	0903      	lsrs	r3, r0, #4
 80001cc:	428b      	cmp	r3, r1
 80001ce:	d301      	bcc.n	80001d4 <__udivsi3+0xcc>
 80001d0:	010b      	lsls	r3, r1, #4
 80001d2:	1ac0      	subs	r0, r0, r3
 80001d4:	4152      	adcs	r2, r2
 80001d6:	08c3      	lsrs	r3, r0, #3
 80001d8:	428b      	cmp	r3, r1
 80001da:	d301      	bcc.n	80001e0 <__udivsi3+0xd8>
 80001dc:	00cb      	lsls	r3, r1, #3
 80001de:	1ac0      	subs	r0, r0, r3
 80001e0:	4152      	adcs	r2, r2
 80001e2:	0883      	lsrs	r3, r0, #2
 80001e4:	428b      	cmp	r3, r1
 80001e6:	d301      	bcc.n	80001ec <__udivsi3+0xe4>
 80001e8:	008b      	lsls	r3, r1, #2
 80001ea:	1ac0      	subs	r0, r0, r3
 80001ec:	4152      	adcs	r2, r2
 80001ee:	0843      	lsrs	r3, r0, #1
 80001f0:	428b      	cmp	r3, r1
 80001f2:	d301      	bcc.n	80001f8 <__udivsi3+0xf0>
 80001f4:	004b      	lsls	r3, r1, #1
 80001f6:	1ac0      	subs	r0, r0, r3
 80001f8:	4152      	adcs	r2, r2
 80001fa:	1a41      	subs	r1, r0, r1
 80001fc:	d200      	bcs.n	8000200 <__udivsi3+0xf8>
 80001fe:	4601      	mov	r1, r0
 8000200:	4152      	adcs	r2, r2
 8000202:	4610      	mov	r0, r2
 8000204:	4770      	bx	lr
 8000206:	e7ff      	b.n	8000208 <__udivsi3+0x100>
 8000208:	b501      	push	{r0, lr}
 800020a:	2000      	movs	r0, #0
 800020c:	f000 f8f0 	bl	80003f0 <__aeabi_idiv0>
 8000210:	bd02      	pop	{r1, pc}
 8000212:	46c0      	nop			; (mov r8, r8)

08000214 <__aeabi_uidivmod>:
 8000214:	2900      	cmp	r1, #0
 8000216:	d0f7      	beq.n	8000208 <__udivsi3+0x100>
 8000218:	e776      	b.n	8000108 <__udivsi3>
 800021a:	4770      	bx	lr

0800021c <__divsi3>:
 800021c:	4603      	mov	r3, r0
 800021e:	430b      	orrs	r3, r1
 8000220:	d47f      	bmi.n	8000322 <__divsi3+0x106>
 8000222:	2200      	movs	r2, #0
 8000224:	0843      	lsrs	r3, r0, #1
 8000226:	428b      	cmp	r3, r1
 8000228:	d374      	bcc.n	8000314 <__divsi3+0xf8>
 800022a:	0903      	lsrs	r3, r0, #4
 800022c:	428b      	cmp	r3, r1
 800022e:	d35f      	bcc.n	80002f0 <__divsi3+0xd4>
 8000230:	0a03      	lsrs	r3, r0, #8
 8000232:	428b      	cmp	r3, r1
 8000234:	d344      	bcc.n	80002c0 <__divsi3+0xa4>
 8000236:	0b03      	lsrs	r3, r0, #12
 8000238:	428b      	cmp	r3, r1
 800023a:	d328      	bcc.n	800028e <__divsi3+0x72>
 800023c:	0c03      	lsrs	r3, r0, #16
 800023e:	428b      	cmp	r3, r1
 8000240:	d30d      	bcc.n	800025e <__divsi3+0x42>
 8000242:	22ff      	movs	r2, #255	; 0xff
 8000244:	0209      	lsls	r1, r1, #8
 8000246:	ba12      	rev	r2, r2
 8000248:	0c03      	lsrs	r3, r0, #16
 800024a:	428b      	cmp	r3, r1
 800024c:	d302      	bcc.n	8000254 <__divsi3+0x38>
 800024e:	1212      	asrs	r2, r2, #8
 8000250:	0209      	lsls	r1, r1, #8
 8000252:	d065      	beq.n	8000320 <__divsi3+0x104>
 8000254:	0b03      	lsrs	r3, r0, #12
 8000256:	428b      	cmp	r3, r1
 8000258:	d319      	bcc.n	800028e <__divsi3+0x72>
 800025a:	e000      	b.n	800025e <__divsi3+0x42>
 800025c:	0a09      	lsrs	r1, r1, #8
 800025e:	0bc3      	lsrs	r3, r0, #15
 8000260:	428b      	cmp	r3, r1
 8000262:	d301      	bcc.n	8000268 <__divsi3+0x4c>
 8000264:	03cb      	lsls	r3, r1, #15
 8000266:	1ac0      	subs	r0, r0, r3
 8000268:	4152      	adcs	r2, r2
 800026a:	0b83      	lsrs	r3, r0, #14
 800026c:	428b      	cmp	r3, r1
 800026e:	d301      	bcc.n	8000274 <__divsi3+0x58>
 8000270:	038b      	lsls	r3, r1, #14
 8000272:	1ac0      	subs	r0, r0, r3
 8000274:	4152      	adcs	r2, r2
 8000276:	0b43      	lsrs	r3, r0, #13
 8000278:	428b      	cmp	r3, r1
 800027a:	d301      	bcc.n	8000280 <__divsi3+0x64>
 800027c:	034b      	lsls	r3, r1, #13
 800027e:	1ac0      	subs	r0, r0, r3
 8000280:	4152      	adcs	r2, r2
 8000282:	0b03      	lsrs	r3, r0, #12
 8000284:	428b      	cmp	r3, r1
 8000286:	d301      	bcc.n	800028c <__divsi3+0x70>
 8000288:	030b      	lsls	r3, r1, #12
 800028a:	1ac0      	subs	r0, r0, r3
 800028c:	4152      	adcs	r2, r2
 800028e:	0ac3      	lsrs	r3, r0, #11
 8000290:	428b      	cmp	r3, r1
 8000292:	d301      	bcc.n	8000298 <__divsi3+0x7c>
 8000294:	02cb      	lsls	r3, r1, #11
 8000296:	1ac0      	subs	r0, r0, r3
 8000298:	4152      	adcs	r2, r2
 800029a:	0a83      	lsrs	r3, r0, #10
 800029c:	428b      	cmp	r3, r1
 800029e:	d301      	bcc.n	80002a4 <__divsi3+0x88>
 80002a0:	028b      	lsls	r3, r1, #10
 80002a2:	1ac0      	subs	r0, r0, r3
 80002a4:	4152      	adcs	r2, r2
 80002a6:	0a43      	lsrs	r3, r0, #9
 80002a8:	428b      	cmp	r3, r1
 80002aa:	d301      	bcc.n	80002b0 <__divsi3+0x94>
 80002ac:	024b      	lsls	r3, r1, #9
 80002ae:	1ac0      	subs	r0, r0, r3
 80002b0:	4152      	adcs	r2, r2
 80002b2:	0a03      	lsrs	r3, r0, #8
 80002b4:	428b      	cmp	r3, r1
 80002b6:	d301      	bcc.n	80002bc <__divsi3+0xa0>
 80002b8:	020b      	lsls	r3, r1, #8
 80002ba:	1ac0      	subs	r0, r0, r3
 80002bc:	4152      	adcs	r2, r2
 80002be:	d2cd      	bcs.n	800025c <__divsi3+0x40>
 80002c0:	09c3      	lsrs	r3, r0, #7
 80002c2:	428b      	cmp	r3, r1
 80002c4:	d301      	bcc.n	80002ca <__divsi3+0xae>
 80002c6:	01cb      	lsls	r3, r1, #7
 80002c8:	1ac0      	subs	r0, r0, r3
 80002ca:	4152      	adcs	r2, r2
 80002cc:	0983      	lsrs	r3, r0, #6
 80002ce:	428b      	cmp	r3, r1
 80002d0:	d301      	bcc.n	80002d6 <__divsi3+0xba>
 80002d2:	018b      	lsls	r3, r1, #6
 80002d4:	1ac0      	subs	r0, r0, r3
 80002d6:	4152      	adcs	r2, r2
 80002d8:	0943      	lsrs	r3, r0, #5
 80002da:	428b      	cmp	r3, r1
 80002dc:	d301      	bcc.n	80002e2 <__divsi3+0xc6>
 80002de:	014b      	lsls	r3, r1, #5
 80002e0:	1ac0      	subs	r0, r0, r3
 80002e2:	4152      	adcs	r2, r2
 80002e4:	0903      	lsrs	r3, r0, #4
 80002e6:	428b      	cmp	r3, r1
 80002e8:	d301      	bcc.n	80002ee <__divsi3+0xd2>
 80002ea:	010b      	lsls	r3, r1, #4
 80002ec:	1ac0      	subs	r0, r0, r3
 80002ee:	4152      	adcs	r2, r2
 80002f0:	08c3      	lsrs	r3, r0, #3
 80002f2:	428b      	cmp	r3, r1
 80002f4:	d301      	bcc.n	80002fa <__divsi3+0xde>
 80002f6:	00cb      	lsls	r3, r1, #3
 80002f8:	1ac0      	subs	r0, r0, r3
 80002fa:	4152      	adcs	r2, r2
 80002fc:	0883      	lsrs	r3, r0, #2
 80002fe:	428b      	cmp	r3, r1
 8000300:	d301      	bcc.n	8000306 <__divsi3+0xea>
 8000302:	008b      	lsls	r3, r1, #2
 8000304:	1ac0      	subs	r0, r0, r3
 8000306:	4152      	adcs	r2, r2
 8000308:	0843      	lsrs	r3, r0, #1
 800030a:	428b      	cmp	r3, r1
 800030c:	d301      	bcc.n	8000312 <__divsi3+0xf6>
 800030e:	004b      	lsls	r3, r1, #1
 8000310:	1ac0      	subs	r0, r0, r3
 8000312:	4152      	adcs	r2, r2
 8000314:	1a41      	subs	r1, r0, r1
 8000316:	d200      	bcs.n	800031a <__divsi3+0xfe>
 8000318:	4601      	mov	r1, r0
 800031a:	4152      	adcs	r2, r2
 800031c:	4610      	mov	r0, r2
 800031e:	4770      	bx	lr
 8000320:	e05d      	b.n	80003de <__divsi3+0x1c2>
 8000322:	0fca      	lsrs	r2, r1, #31
 8000324:	d000      	beq.n	8000328 <__divsi3+0x10c>
 8000326:	4249      	negs	r1, r1
 8000328:	1003      	asrs	r3, r0, #32
 800032a:	d300      	bcc.n	800032e <__divsi3+0x112>
 800032c:	4240      	negs	r0, r0
 800032e:	4053      	eors	r3, r2
 8000330:	2200      	movs	r2, #0
 8000332:	469c      	mov	ip, r3
 8000334:	0903      	lsrs	r3, r0, #4
 8000336:	428b      	cmp	r3, r1
 8000338:	d32d      	bcc.n	8000396 <__divsi3+0x17a>
 800033a:	0a03      	lsrs	r3, r0, #8
 800033c:	428b      	cmp	r3, r1
 800033e:	d312      	bcc.n	8000366 <__divsi3+0x14a>
 8000340:	22fc      	movs	r2, #252	; 0xfc
 8000342:	0189      	lsls	r1, r1, #6
 8000344:	ba12      	rev	r2, r2
 8000346:	0a03      	lsrs	r3, r0, #8
 8000348:	428b      	cmp	r3, r1
 800034a:	d30c      	bcc.n	8000366 <__divsi3+0x14a>
 800034c:	0189      	lsls	r1, r1, #6
 800034e:	1192      	asrs	r2, r2, #6
 8000350:	428b      	cmp	r3, r1
 8000352:	d308      	bcc.n	8000366 <__divsi3+0x14a>
 8000354:	0189      	lsls	r1, r1, #6
 8000356:	1192      	asrs	r2, r2, #6
 8000358:	428b      	cmp	r3, r1
 800035a:	d304      	bcc.n	8000366 <__divsi3+0x14a>
 800035c:	0189      	lsls	r1, r1, #6
 800035e:	d03a      	beq.n	80003d6 <__divsi3+0x1ba>
 8000360:	1192      	asrs	r2, r2, #6
 8000362:	e000      	b.n	8000366 <__divsi3+0x14a>
 8000364:	0989      	lsrs	r1, r1, #6
 8000366:	09c3      	lsrs	r3, r0, #7
 8000368:	428b      	cmp	r3, r1
 800036a:	d301      	bcc.n	8000370 <__divsi3+0x154>
 800036c:	01cb      	lsls	r3, r1, #7
 800036e:	1ac0      	subs	r0, r0, r3
 8000370:	4152      	adcs	r2, r2
 8000372:	0983      	lsrs	r3, r0, #6
 8000374:	428b      	cmp	r3, r1
 8000376:	d301      	bcc.n	800037c <__divsi3+0x160>
 8000378:	018b      	lsls	r3, r1, #6
 800037a:	1ac0      	subs	r0, r0, r3
 800037c:	4152      	adcs	r2, r2
 800037e:	0943      	lsrs	r3, r0, #5
 8000380:	428b      	cmp	r3, r1
 8000382:	d301      	bcc.n	8000388 <__divsi3+0x16c>
 8000384:	014b      	lsls	r3, r1, #5
 8000386:	1ac0      	subs	r0, r0, r3
 8000388:	4152      	adcs	r2, r2
 800038a:	0903      	lsrs	r3, r0, #4
 800038c:	428b      	cmp	r3, r1
 800038e:	d301      	bcc.n	8000394 <__divsi3+0x178>
 8000390:	010b      	lsls	r3, r1, #4
 8000392:	1ac0      	subs	r0, r0, r3
 8000394:	4152      	adcs	r2, r2
 8000396:	08c3      	lsrs	r3, r0, #3
 8000398:	428b      	cmp	r3, r1
 800039a:	d301      	bcc.n	80003a0 <__divsi3+0x184>
 800039c:	00cb      	lsls	r3, r1, #3
 800039e:	1ac0      	subs	r0, r0, r3
 80003a0:	4152      	adcs	r2, r2
 80003a2:	0883      	lsrs	r3, r0, #2
 80003a4:	428b      	cmp	r3, r1
 80003a6:	d301      	bcc.n	80003ac <__divsi3+0x190>
 80003a8:	008b      	lsls	r3, r1, #2
 80003aa:	1ac0      	subs	r0, r0, r3
 80003ac:	4152      	adcs	r2, r2
 80003ae:	d2d9      	bcs.n	8000364 <__divsi3+0x148>
 80003b0:	0843      	lsrs	r3, r0, #1
 80003b2:	428b      	cmp	r3, r1
 80003b4:	d301      	bcc.n	80003ba <__divsi3+0x19e>
 80003b6:	004b      	lsls	r3, r1, #1
 80003b8:	1ac0      	subs	r0, r0, r3
 80003ba:	4152      	adcs	r2, r2
 80003bc:	1a41      	subs	r1, r0, r1
 80003be:	d200      	bcs.n	80003c2 <__divsi3+0x1a6>
 80003c0:	4601      	mov	r1, r0
 80003c2:	4663      	mov	r3, ip
 80003c4:	4152      	adcs	r2, r2
 80003c6:	105b      	asrs	r3, r3, #1
 80003c8:	4610      	mov	r0, r2
 80003ca:	d301      	bcc.n	80003d0 <__divsi3+0x1b4>
 80003cc:	4240      	negs	r0, r0
 80003ce:	2b00      	cmp	r3, #0
 80003d0:	d500      	bpl.n	80003d4 <__divsi3+0x1b8>
 80003d2:	4249      	negs	r1, r1
 80003d4:	4770      	bx	lr
 80003d6:	4663      	mov	r3, ip
 80003d8:	105b      	asrs	r3, r3, #1
 80003da:	d300      	bcc.n	80003de <__divsi3+0x1c2>
 80003dc:	4240      	negs	r0, r0
 80003de:	b501      	push	{r0, lr}
 80003e0:	2000      	movs	r0, #0
 80003e2:	f000 f805 	bl	80003f0 <__aeabi_idiv0>
 80003e6:	bd02      	pop	{r1, pc}

080003e8 <__aeabi_idivmod>:
 80003e8:	2900      	cmp	r1, #0
 80003ea:	d0f8      	beq.n	80003de <__divsi3+0x1c2>
 80003ec:	e716      	b.n	800021c <__divsi3>
 80003ee:	4770      	bx	lr

080003f0 <__aeabi_idiv0>:
 80003f0:	4770      	bx	lr
 80003f2:	46c0      	nop			; (mov r8, r8)

080003f4 <maincpp>:
volatile uint16_t pwm2freqnew = 10000;
volatile uint16_t val;
volatile uint32_t pwm1counter;
volatile uint32_t pwm1period;
void maincpp()
{
 80003f4:	b510      	push	{r4, lr}

	HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1);
 80003f6:	2100      	movs	r1, #0
 80003f8:	4819      	ldr	r0, [pc, #100]	; (8000460 <maincpp+0x6c>)
 80003fa:	f001 fa39 	bl	8001870 <HAL_TIM_PWM_Start>
 80003fe:	e011      	b.n	8000424 <maincpp+0x30>
			htim1.Instance->ARR = pwm1freq;

		}
		if(pwm2freq != pwm2freqnew)
		{
			val = (360000/pwm2freqnew)-1;
 8000400:	4c18      	ldr	r4, [pc, #96]	; (8000464 <maincpp+0x70>)
 8000402:	8821      	ldrh	r1, [r4, #0]
 8000404:	b289      	uxth	r1, r1
 8000406:	4818      	ldr	r0, [pc, #96]	; (8000468 <maincpp+0x74>)
 8000408:	f7ff ff08 	bl	800021c <__divsi3>
 800040c:	3801      	subs	r0, #1
 800040e:	b280      	uxth	r0, r0
 8000410:	4b16      	ldr	r3, [pc, #88]	; (800046c <maincpp+0x78>)
 8000412:	8018      	strh	r0, [r3, #0]
			pwm1freqnew = val;
 8000414:	881b      	ldrh	r3, [r3, #0]
 8000416:	b29b      	uxth	r3, r3
 8000418:	4a15      	ldr	r2, [pc, #84]	; (8000470 <maincpp+0x7c>)
 800041a:	8013      	strh	r3, [r2, #0]
			pwm2freq = pwm2freqnew;
 800041c:	8823      	ldrh	r3, [r4, #0]
 800041e:	b29b      	uxth	r3, r3
 8000420:	4a14      	ldr	r2, [pc, #80]	; (8000474 <maincpp+0x80>)
 8000422:	8013      	strh	r3, [r2, #0]
		if(pwm1freq != pwm1freqnew)
 8000424:	4b14      	ldr	r3, [pc, #80]	; (8000478 <maincpp+0x84>)
 8000426:	881a      	ldrh	r2, [r3, #0]
 8000428:	b292      	uxth	r2, r2
 800042a:	4b11      	ldr	r3, [pc, #68]	; (8000470 <maincpp+0x7c>)
 800042c:	881b      	ldrh	r3, [r3, #0]
 800042e:	b29b      	uxth	r3, r3
 8000430:	429a      	cmp	r2, r3
 8000432:	d00c      	beq.n	800044e <maincpp+0x5a>
			pwm1freq = pwm1freqnew;
 8000434:	4b0e      	ldr	r3, [pc, #56]	; (8000470 <maincpp+0x7c>)
 8000436:	881a      	ldrh	r2, [r3, #0]
 8000438:	b292      	uxth	r2, r2
 800043a:	4b0f      	ldr	r3, [pc, #60]	; (8000478 <maincpp+0x84>)
 800043c:	801a      	strh	r2, [r3, #0]
			htim1.Instance->CCR1 = (pwm1freq/2);
 800043e:	881a      	ldrh	r2, [r3, #0]
 8000440:	4907      	ldr	r1, [pc, #28]	; (8000460 <maincpp+0x6c>)
 8000442:	6809      	ldr	r1, [r1, #0]
 8000444:	0852      	lsrs	r2, r2, #1
 8000446:	634a      	str	r2, [r1, #52]	; 0x34
			htim1.Instance->ARR = pwm1freq;
 8000448:	881b      	ldrh	r3, [r3, #0]
 800044a:	b29b      	uxth	r3, r3
 800044c:	62cb      	str	r3, [r1, #44]	; 0x2c
		if(pwm2freq != pwm2freqnew)
 800044e:	4b09      	ldr	r3, [pc, #36]	; (8000474 <maincpp+0x80>)
 8000450:	881a      	ldrh	r2, [r3, #0]
 8000452:	b292      	uxth	r2, r2
 8000454:	4b03      	ldr	r3, [pc, #12]	; (8000464 <maincpp+0x70>)
 8000456:	881b      	ldrh	r3, [r3, #0]
 8000458:	b29b      	uxth	r3, r3
 800045a:	429a      	cmp	r2, r3
 800045c:	d1d0      	bne.n	8000400 <maincpp+0xc>
 800045e:	e7e1      	b.n	8000424 <maincpp+0x30>
 8000460:	20000098 	.word	0x20000098
 8000464:	20000002 	.word	0x20000002
 8000468:	00057e40 	.word	0x00057e40
 800046c:	20000030 	.word	0x20000030
 8000470:	20000000 	.word	0x20000000
 8000474:	2000002e 	.word	0x2000002e
 8000478:	2000002c 	.word	0x2000002c

0800047c <MX_GPIO_Init>:
/* USER CODE END 1 */

/** Configure pins
*/
void MX_GPIO_Init(void)
{
 800047c:	b5f0      	push	{r4, r5, r6, r7, lr}
 800047e:	46c6      	mov	lr, r8
 8000480:	b500      	push	{lr}
 8000482:	b088      	sub	sp, #32

  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000484:	2214      	movs	r2, #20
 8000486:	2100      	movs	r1, #0
 8000488:	a803      	add	r0, sp, #12
 800048a:	f001 faeb 	bl	8001a64 <memset>

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOF_CLK_ENABLE();
 800048e:	4b2a      	ldr	r3, [pc, #168]	; (8000538 <MX_GPIO_Init+0xbc>)
 8000490:	6959      	ldr	r1, [r3, #20]
 8000492:	2080      	movs	r0, #128	; 0x80
 8000494:	03c0      	lsls	r0, r0, #15
 8000496:	4301      	orrs	r1, r0
 8000498:	6159      	str	r1, [r3, #20]
 800049a:	695a      	ldr	r2, [r3, #20]
 800049c:	4002      	ands	r2, r0
 800049e:	9200      	str	r2, [sp, #0]
 80004a0:	9a00      	ldr	r2, [sp, #0]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 80004a2:	6959      	ldr	r1, [r3, #20]
 80004a4:	2080      	movs	r0, #128	; 0x80
 80004a6:	0280      	lsls	r0, r0, #10
 80004a8:	4301      	orrs	r1, r0
 80004aa:	6159      	str	r1, [r3, #20]
 80004ac:	695a      	ldr	r2, [r3, #20]
 80004ae:	4002      	ands	r2, r0
 80004b0:	9201      	str	r2, [sp, #4]
 80004b2:	9a01      	ldr	r2, [sp, #4]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 80004b4:	695a      	ldr	r2, [r3, #20]
 80004b6:	2180      	movs	r1, #128	; 0x80
 80004b8:	02c9      	lsls	r1, r1, #11
 80004ba:	430a      	orrs	r2, r1
 80004bc:	615a      	str	r2, [r3, #20]
 80004be:	695b      	ldr	r3, [r3, #20]
 80004c0:	400b      	ands	r3, r1
 80004c2:	9302      	str	r3, [sp, #8]
 80004c4:	9b02      	ldr	r3, [sp, #8]

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOA, ENC_RST_Pin|ENC_CS_Pin, GPIO_PIN_RESET);
 80004c6:	2390      	movs	r3, #144	; 0x90
 80004c8:	05db      	lsls	r3, r3, #23
 80004ca:	4698      	mov	r8, r3
 80004cc:	2200      	movs	r2, #0
 80004ce:	2118      	movs	r1, #24
 80004d0:	0018      	movs	r0, r3
 80004d2:	f000 fb41 	bl	8000b58 <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(LED1_GPIO_Port, LED1_Pin, GPIO_PIN_RESET);
 80004d6:	4d19      	ldr	r5, [pc, #100]	; (800053c <MX_GPIO_Init+0xc0>)
 80004d8:	2200      	movs	r2, #0
 80004da:	2102      	movs	r1, #2
 80004dc:	0028      	movs	r0, r5
 80004de:	f000 fb3b 	bl	8000b58 <HAL_GPIO_WritePin>

  /*Configure GPIO pin : PF1 */
  GPIO_InitStruct.Pin = GPIO_PIN_1;
 80004e2:	2702      	movs	r7, #2
 80004e4:	9703      	str	r7, [sp, #12]
  GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING;
 80004e6:	2388      	movs	r3, #136	; 0x88
 80004e8:	035b      	lsls	r3, r3, #13
 80004ea:	9304      	str	r3, [sp, #16]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 80004ec:	2400      	movs	r4, #0
 80004ee:	9405      	str	r4, [sp, #20]
  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
 80004f0:	a903      	add	r1, sp, #12
 80004f2:	4813      	ldr	r0, [pc, #76]	; (8000540 <MX_GPIO_Init+0xc4>)
 80004f4:	f000 fa6a 	bl	80009cc <HAL_GPIO_Init>

  /*Configure GPIO pins : PAPin PAPin */
  GPIO_InitStruct.Pin = ENC_RST_Pin|ENC_CS_Pin;
 80004f8:	2318      	movs	r3, #24
 80004fa:	9303      	str	r3, [sp, #12]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 80004fc:	2601      	movs	r6, #1
 80004fe:	9604      	str	r6, [sp, #16]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000500:	9405      	str	r4, [sp, #20]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 8000502:	9406      	str	r4, [sp, #24]
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8000504:	a903      	add	r1, sp, #12
 8000506:	4640      	mov	r0, r8
 8000508:	f000 fa60 	bl	80009cc <HAL_GPIO_Init>

  /*Configure GPIO pin : PtPin */
  GPIO_InitStruct.Pin = LED1_Pin;
 800050c:	9703      	str	r7, [sp, #12]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 800050e:	9604      	str	r6, [sp, #16]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000510:	9405      	str	r4, [sp, #20]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 8000512:	2303      	movs	r3, #3
 8000514:	9306      	str	r3, [sp, #24]
  HAL_GPIO_Init(LED1_GPIO_Port, &GPIO_InitStruct);
 8000516:	a903      	add	r1, sp, #12
 8000518:	0028      	movs	r0, r5
 800051a:	f000 fa57 	bl	80009cc <HAL_GPIO_Init>

  /* EXTI interrupt init*/
  HAL_NVIC_SetPriority(EXTI0_1_IRQn, 0, 0);
 800051e:	2200      	movs	r2, #0
 8000520:	2100      	movs	r1, #0
 8000522:	2005      	movs	r0, #5
 8000524:	f000 f9fa 	bl	800091c <HAL_NVIC_SetPriority>
  HAL_NVIC_EnableIRQ(EXTI0_1_IRQn);
 8000528:	2005      	movs	r0, #5
 800052a:	f000 fa27 	bl	800097c <HAL_NVIC_EnableIRQ>

}
 800052e:	b008      	add	sp, #32
 8000530:	bc80      	pop	{r7}
 8000532:	46b8      	mov	r8, r7
 8000534:	bdf0      	pop	{r4, r5, r6, r7, pc}
 8000536:	46c0      	nop			; (mov r8, r8)
 8000538:	40021000 	.word	0x40021000
 800053c:	48000400 	.word	0x48000400
 8000540:	48001400 	.word	0x48001400

08000544 <Error_Handler>:
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __disable_irq(void)
{
  __ASM volatile ("cpsid i" : : : "memory");
 8000544:	b672      	cpsid	i
void Error_Handler(void)
{
  /* USER CODE BEGIN Error_Handler_Debug */
  /* User can add his own implementation to report the HAL error return state */
  __disable_irq();
  while (1)
 8000546:	e7fe      	b.n	8000546 <Error_Handler+0x2>

08000548 <SystemClock_Config>:
{
 8000548:	b500      	push	{lr}
 800054a:	b091      	sub	sp, #68	; 0x44
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 800054c:	2230      	movs	r2, #48	; 0x30
 800054e:	2100      	movs	r1, #0
 8000550:	a804      	add	r0, sp, #16
 8000552:	f001 fa87 	bl	8001a64 <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 8000556:	2210      	movs	r2, #16
 8000558:	2100      	movs	r1, #0
 800055a:	4668      	mov	r0, sp
 800055c:	f001 fa82 	bl	8001a64 <memset>
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8000560:	2302      	movs	r3, #2
 8000562:	9304      	str	r3, [sp, #16]
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 8000564:	2201      	movs	r2, #1
 8000566:	9207      	str	r2, [sp, #28]
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8000568:	320f      	adds	r2, #15
 800056a:	9208      	str	r2, [sp, #32]
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 800056c:	930c      	str	r3, [sp, #48]	; 0x30
  RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
 800056e:	23e0      	movs	r3, #224	; 0xe0
 8000570:	035b      	lsls	r3, r3, #13
 8000572:	930e      	str	r3, [sp, #56]	; 0x38
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 8000574:	a804      	add	r0, sp, #16
 8000576:	f000 fb05 	bl	8000b84 <HAL_RCC_OscConfig>
 800057a:	2800      	cmp	r0, #0
 800057c:	d10e      	bne.n	800059c <SystemClock_Config+0x54>
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 800057e:	2307      	movs	r3, #7
 8000580:	9300      	str	r3, [sp, #0]
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 8000582:	3b05      	subs	r3, #5
 8000584:	9301      	str	r3, [sp, #4]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 8000586:	2300      	movs	r3, #0
 8000588:	9302      	str	r3, [sp, #8]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 800058a:	9303      	str	r3, [sp, #12]
  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
 800058c:	2101      	movs	r1, #1
 800058e:	4668      	mov	r0, sp
 8000590:	f000 fd7e 	bl	8001090 <HAL_RCC_ClockConfig>
 8000594:	2800      	cmp	r0, #0
 8000596:	d103      	bne.n	80005a0 <SystemClock_Config+0x58>
}
 8000598:	b011      	add	sp, #68	; 0x44
 800059a:	bd00      	pop	{pc}
    Error_Handler();
 800059c:	f7ff ffd2 	bl	8000544 <Error_Handler>
    Error_Handler();
 80005a0:	f7ff ffd0 	bl	8000544 <Error_Handler>

080005a4 <main>:
{
 80005a4:	b510      	push	{r4, lr}
  HAL_Init();
 80005a6:	f000 f997 	bl	80008d8 <HAL_Init>
  SystemClock_Config();
 80005aa:	f7ff ffcd 	bl	8000548 <SystemClock_Config>
  MX_GPIO_Init();
 80005ae:	f7ff ff65 	bl	800047c <MX_GPIO_Init>
  MX_SPI1_Init();
 80005b2:	f000 f805 	bl	80005c0 <MX_SPI1_Init>
  MX_TIM1_Init();
 80005b6:	f000 f8c1 	bl	800073c <MX_TIM1_Init>
  maincpp();
 80005ba:	f7ff ff1b 	bl	80003f4 <maincpp>
  while (1)
 80005be:	e7fe      	b.n	80005be <main+0x1a>

080005c0 <MX_SPI1_Init>:

SPI_HandleTypeDef hspi1;

/* SPI1 init function */
void MX_SPI1_Init(void)
{
 80005c0:	b510      	push	{r4, lr}
  /* USER CODE END SPI1_Init 0 */

  /* USER CODE BEGIN SPI1_Init 1 */

  /* USER CODE END SPI1_Init 1 */
  hspi1.Instance = SPI1;
 80005c2:	4811      	ldr	r0, [pc, #68]	; (8000608 <MX_SPI1_Init+0x48>)
 80005c4:	4b11      	ldr	r3, [pc, #68]	; (800060c <MX_SPI1_Init+0x4c>)
 80005c6:	6003      	str	r3, [r0, #0]
  hspi1.Init.Mode = SPI_MODE_MASTER;
 80005c8:	2382      	movs	r3, #130	; 0x82
 80005ca:	005b      	lsls	r3, r3, #1
 80005cc:	6043      	str	r3, [r0, #4]
  hspi1.Init.Direction = SPI_DIRECTION_2LINES;
 80005ce:	2300      	movs	r3, #0
 80005d0:	6083      	str	r3, [r0, #8]
  hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
 80005d2:	22e0      	movs	r2, #224	; 0xe0
 80005d4:	00d2      	lsls	r2, r2, #3
 80005d6:	60c2      	str	r2, [r0, #12]
  hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
 80005d8:	6103      	str	r3, [r0, #16]
  hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
 80005da:	6143      	str	r3, [r0, #20]
  hspi1.Init.NSS = SPI_NSS_SOFT;
 80005dc:	2280      	movs	r2, #128	; 0x80
 80005de:	0092      	lsls	r2, r2, #2
 80005e0:	6182      	str	r2, [r0, #24]
  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
 80005e2:	61c3      	str	r3, [r0, #28]
  hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
 80005e4:	6203      	str	r3, [r0, #32]
  hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
 80005e6:	6243      	str	r3, [r0, #36]	; 0x24
  hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
 80005e8:	6283      	str	r3, [r0, #40]	; 0x28
  hspi1.Init.CRCPolynomial = 7;
 80005ea:	3afa      	subs	r2, #250	; 0xfa
 80005ec:	3aff      	subs	r2, #255	; 0xff
 80005ee:	62c2      	str	r2, [r0, #44]	; 0x2c
  hspi1.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE;
 80005f0:	6303      	str	r3, [r0, #48]	; 0x30
  hspi1.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;
 80005f2:	3308      	adds	r3, #8
 80005f4:	6343      	str	r3, [r0, #52]	; 0x34
  if (HAL_SPI_Init(&hspi1) != HAL_OK)
 80005f6:	f000 fde5 	bl	80011c4 <HAL_SPI_Init>
 80005fa:	2800      	cmp	r0, #0
 80005fc:	d100      	bne.n	8000600 <MX_SPI1_Init+0x40>
  }
  /* USER CODE BEGIN SPI1_Init 2 */

  /* USER CODE END SPI1_Init 2 */

}
 80005fe:	bd10      	pop	{r4, pc}
    Error_Handler();
 8000600:	f7ff ffa0 	bl	8000544 <Error_Handler>
}
 8000604:	e7fb      	b.n	80005fe <MX_SPI1_Init+0x3e>
 8000606:	46c0      	nop			; (mov r8, r8)
 8000608:	20000034 	.word	0x20000034
 800060c:	40013000 	.word	0x40013000

08000610 <HAL_SPI_MspInit>:

void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
{
 8000610:	b510      	push	{r4, lr}
 8000612:	b088      	sub	sp, #32
 8000614:	0004      	movs	r4, r0

  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000616:	2214      	movs	r2, #20
 8000618:	2100      	movs	r1, #0
 800061a:	a803      	add	r0, sp, #12
 800061c:	f001 fa22 	bl	8001a64 <memset>
  if(spiHandle->Instance==SPI1)
 8000620:	6822      	ldr	r2, [r4, #0]
 8000622:	4b12      	ldr	r3, [pc, #72]	; (800066c <HAL_SPI_MspInit+0x5c>)
 8000624:	429a      	cmp	r2, r3
 8000626:	d001      	beq.n	800062c <HAL_SPI_MspInit+0x1c>

  /* USER CODE BEGIN SPI1_MspInit 1 */

  /* USER CODE END SPI1_MspInit 1 */
  }
}
 8000628:	b008      	add	sp, #32
 800062a:	bd10      	pop	{r4, pc}
    __HAL_RCC_SPI1_CLK_ENABLE();
 800062c:	4b10      	ldr	r3, [pc, #64]	; (8000670 <HAL_SPI_MspInit+0x60>)
 800062e:	6999      	ldr	r1, [r3, #24]
 8000630:	2080      	movs	r0, #128	; 0x80
 8000632:	0140      	lsls	r0, r0, #5
 8000634:	4301      	orrs	r1, r0
 8000636:	6199      	str	r1, [r3, #24]
 8000638:	699a      	ldr	r2, [r3, #24]
 800063a:	4002      	ands	r2, r0
 800063c:	9201      	str	r2, [sp, #4]
 800063e:	9a01      	ldr	r2, [sp, #4]
    __HAL_RCC_GPIOA_CLK_ENABLE();
 8000640:	695a      	ldr	r2, [r3, #20]
 8000642:	2180      	movs	r1, #128	; 0x80
 8000644:	0289      	lsls	r1, r1, #10
 8000646:	430a      	orrs	r2, r1
 8000648:	615a      	str	r2, [r3, #20]
 800064a:	695b      	ldr	r3, [r3, #20]
 800064c:	400b      	ands	r3, r1
 800064e:	9302      	str	r3, [sp, #8]
 8000650:	9b02      	ldr	r3, [sp, #8]
    GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
 8000652:	23e0      	movs	r3, #224	; 0xe0
 8000654:	9303      	str	r3, [sp, #12]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8000656:	3bde      	subs	r3, #222	; 0xde
 8000658:	9304      	str	r3, [sp, #16]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 800065a:	3301      	adds	r3, #1
 800065c:	9306      	str	r3, [sp, #24]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800065e:	2090      	movs	r0, #144	; 0x90
 8000660:	a903      	add	r1, sp, #12
 8000662:	05c0      	lsls	r0, r0, #23
 8000664:	f000 f9b2 	bl	80009cc <HAL_GPIO_Init>
}
 8000668:	e7de      	b.n	8000628 <HAL_SPI_MspInit+0x18>
 800066a:	46c0      	nop			; (mov r8, r8)
 800066c:	40013000 	.word	0x40013000
 8000670:	40021000 	.word	0x40021000

08000674 <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 8000674:	b082      	sub	sp, #8
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_SYSCFG_CLK_ENABLE();
 8000676:	4b0a      	ldr	r3, [pc, #40]	; (80006a0 <HAL_MspInit+0x2c>)
 8000678:	6999      	ldr	r1, [r3, #24]
 800067a:	2201      	movs	r2, #1
 800067c:	4311      	orrs	r1, r2
 800067e:	6199      	str	r1, [r3, #24]
 8000680:	6999      	ldr	r1, [r3, #24]
 8000682:	400a      	ands	r2, r1
 8000684:	9200      	str	r2, [sp, #0]
 8000686:	9a00      	ldr	r2, [sp, #0]
  __HAL_RCC_PWR_CLK_ENABLE();
 8000688:	69da      	ldr	r2, [r3, #28]
 800068a:	2180      	movs	r1, #128	; 0x80
 800068c:	0549      	lsls	r1, r1, #21
 800068e:	430a      	orrs	r2, r1
 8000690:	61da      	str	r2, [r3, #28]
 8000692:	69db      	ldr	r3, [r3, #28]
 8000694:	400b      	ands	r3, r1
 8000696:	9301      	str	r3, [sp, #4]
 8000698:	9b01      	ldr	r3, [sp, #4]
  /* System interrupt init*/

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 800069a:	b002      	add	sp, #8
 800069c:	4770      	bx	lr
 800069e:	46c0      	nop			; (mov r8, r8)
 80006a0:	40021000 	.word	0x40021000

080006a4 <NMI_Handler>:
{
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
  while (1)
 80006a4:	e7fe      	b.n	80006a4 <NMI_Handler>

080006a6 <HardFault_Handler>:
void HardFault_Handler(void)
{
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 80006a6:	e7fe      	b.n	80006a6 <HardFault_Handler>

080006a8 <SVC_Handler>:

  /* USER CODE END SVC_IRQn 0 */
  /* USER CODE BEGIN SVC_IRQn 1 */

  /* USER CODE END SVC_IRQn 1 */
}
 80006a8:	4770      	bx	lr

080006aa <PendSV_Handler>:

  /* USER CODE END PendSV_IRQn 0 */
  /* USER CODE BEGIN PendSV_IRQn 1 */

  /* USER CODE END PendSV_IRQn 1 */
}
 80006aa:	4770      	bx	lr

080006ac <SysTick_Handler>:

/**
  * @brief This function handles System tick timer.
  */
void SysTick_Handler(void)
{
 80006ac:	b510      	push	{r4, lr}
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 80006ae:	f000 f923 	bl	80008f8 <HAL_IncTick>
  /* USER CODE BEGIN SysTick_IRQn 1 */

  /* USER CODE END SysTick_IRQn 1 */
}
 80006b2:	bd10      	pop	{r4, pc}

080006b4 <EXTI0_1_IRQHandler>:

/**
  * @brief This function handles EXTI line 0 and 1 interrupts.
  */
void EXTI0_1_IRQHandler(void)
{
 80006b4:	b510      	push	{r4, lr}
  /* USER CODE BEGIN EXTI0_1_IRQn 0 */

  /* USER CODE END EXTI0_1_IRQn 0 */
  HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_1);
 80006b6:	2002      	movs	r0, #2
 80006b8:	f000 fa56 	bl	8000b68 <HAL_GPIO_EXTI_IRQHandler>
  /* USER CODE BEGIN EXTI0_1_IRQn 1 */

  /* USER CODE END EXTI0_1_IRQn 1 */
}
 80006bc:	bd10      	pop	{r4, pc}

080006be <SystemInit>:
                         before branch to main program. This call is made inside
                         the "startup_stm32f0xx.s" file.
                         User can setups the default system clock (System clock source, PLL Multiplier
                         and Divider factors, AHB/APBx prescalers and Flash settings).
   */
}
 80006be:	4770      	bx	lr

080006c0 <HAL_TIM_Base_MspInit>:
  HAL_TIM_MspPostInit(&htim1);

}

void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
{
 80006c0:	b082      	sub	sp, #8

  if(tim_baseHandle->Instance==TIM1)
 80006c2:	6802      	ldr	r2, [r0, #0]
 80006c4:	4b07      	ldr	r3, [pc, #28]	; (80006e4 <HAL_TIM_Base_MspInit+0x24>)
 80006c6:	429a      	cmp	r2, r3
 80006c8:	d001      	beq.n	80006ce <HAL_TIM_Base_MspInit+0xe>
    __HAL_RCC_TIM1_CLK_ENABLE();
  /* USER CODE BEGIN TIM1_MspInit 1 */

  /* USER CODE END TIM1_MspInit 1 */
  }
}
 80006ca:	b002      	add	sp, #8
 80006cc:	4770      	bx	lr
    __HAL_RCC_TIM1_CLK_ENABLE();
 80006ce:	4a06      	ldr	r2, [pc, #24]	; (80006e8 <HAL_TIM_Base_MspInit+0x28>)
 80006d0:	6991      	ldr	r1, [r2, #24]
 80006d2:	2080      	movs	r0, #128	; 0x80
 80006d4:	0100      	lsls	r0, r0, #4
 80006d6:	4301      	orrs	r1, r0
 80006d8:	6191      	str	r1, [r2, #24]
 80006da:	6993      	ldr	r3, [r2, #24]
 80006dc:	4003      	ands	r3, r0
 80006de:	9301      	str	r3, [sp, #4]
 80006e0:	9b01      	ldr	r3, [sp, #4]
}
 80006e2:	e7f2      	b.n	80006ca <HAL_TIM_Base_MspInit+0xa>
 80006e4:	40012c00 	.word	0x40012c00
 80006e8:	40021000 	.word	0x40021000

080006ec <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)
{
 80006ec:	b510      	push	{r4, lr}
 80006ee:	b086      	sub	sp, #24
 80006f0:	0004      	movs	r4, r0

  GPIO_InitTypeDef GPIO_InitStruct = {0};
 80006f2:	2214      	movs	r2, #20
 80006f4:	2100      	movs	r1, #0
 80006f6:	a801      	add	r0, sp, #4
 80006f8:	f001 f9b4 	bl	8001a64 <memset>
  if(timHandle->Instance==TIM1)
 80006fc:	6822      	ldr	r2, [r4, #0]
 80006fe:	4b0d      	ldr	r3, [pc, #52]	; (8000734 <HAL_TIM_MspPostInit+0x48>)
 8000700:	429a      	cmp	r2, r3
 8000702:	d001      	beq.n	8000708 <HAL_TIM_MspPostInit+0x1c>
  /* USER CODE BEGIN TIM1_MspPostInit 1 */

  /* USER CODE END TIM1_MspPostInit 1 */
  }

}
 8000704:	b006      	add	sp, #24
 8000706:	bd10      	pop	{r4, pc}
    __HAL_RCC_GPIOA_CLK_ENABLE();
 8000708:	4a0b      	ldr	r2, [pc, #44]	; (8000738 <HAL_TIM_MspPostInit+0x4c>)
 800070a:	6951      	ldr	r1, [r2, #20]
 800070c:	2080      	movs	r0, #128	; 0x80
 800070e:	0280      	lsls	r0, r0, #10
 8000710:	4301      	orrs	r1, r0
 8000712:	6151      	str	r1, [r2, #20]
 8000714:	6953      	ldr	r3, [r2, #20]
 8000716:	4003      	ands	r3, r0
 8000718:	9300      	str	r3, [sp, #0]
 800071a:	9b00      	ldr	r3, [sp, #0]
    GPIO_InitStruct.Pin = GPIO_PIN_8;
 800071c:	2380      	movs	r3, #128	; 0x80
 800071e:	005b      	lsls	r3, r3, #1
 8000720:	9301      	str	r3, [sp, #4]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8000722:	3bfe      	subs	r3, #254	; 0xfe
 8000724:	9302      	str	r3, [sp, #8]
    GPIO_InitStruct.Alternate = GPIO_AF2_TIM1;
 8000726:	9305      	str	r3, [sp, #20]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8000728:	2090      	movs	r0, #144	; 0x90
 800072a:	a901      	add	r1, sp, #4
 800072c:	05c0      	lsls	r0, r0, #23
 800072e:	f000 f94d 	bl	80009cc <HAL_GPIO_Init>
}
 8000732:	e7e7      	b.n	8000704 <HAL_TIM_MspPostInit+0x18>
 8000734:	40012c00 	.word	0x40012c00
 8000738:	40021000 	.word	0x40021000

0800073c <MX_TIM1_Init>:
{
 800073c:	b500      	push	{lr}
 800073e:	b097      	sub	sp, #92	; 0x5c
  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
 8000740:	2210      	movs	r2, #16
 8000742:	2100      	movs	r1, #0
 8000744:	a812      	add	r0, sp, #72	; 0x48
 8000746:	f001 f98d 	bl	8001a64 <memset>
  TIM_MasterConfigTypeDef sMasterConfig = {0};
 800074a:	2208      	movs	r2, #8
 800074c:	2100      	movs	r1, #0
 800074e:	a810      	add	r0, sp, #64	; 0x40
 8000750:	f001 f988 	bl	8001a64 <memset>
  TIM_OC_InitTypeDef sConfigOC = {0};
 8000754:	221c      	movs	r2, #28
 8000756:	2100      	movs	r1, #0
 8000758:	a809      	add	r0, sp, #36	; 0x24
 800075a:	f001 f983 	bl	8001a64 <memset>
  TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
 800075e:	2220      	movs	r2, #32
 8000760:	2100      	movs	r1, #0
 8000762:	a801      	add	r0, sp, #4
 8000764:	f001 f97e 	bl	8001a64 <memset>
  htim1.Instance = TIM1;
 8000768:	4830      	ldr	r0, [pc, #192]	; (800082c <MX_TIM1_Init+0xf0>)
 800076a:	4b31      	ldr	r3, [pc, #196]	; (8000830 <MX_TIM1_Init+0xf4>)
 800076c:	6003      	str	r3, [r0, #0]
  htim1.Init.Prescaler = 100-1;
 800076e:	2363      	movs	r3, #99	; 0x63
 8000770:	6043      	str	r3, [r0, #4]
  htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
 8000772:	2300      	movs	r3, #0
 8000774:	6083      	str	r3, [r0, #8]
  htim1.Init.Period = 3600;
 8000776:	22e1      	movs	r2, #225	; 0xe1
 8000778:	0112      	lsls	r2, r2, #4
 800077a:	60c2      	str	r2, [r0, #12]
  htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
 800077c:	6103      	str	r3, [r0, #16]
  htim1.Init.RepetitionCounter = 0;
 800077e:	6143      	str	r3, [r0, #20]
  htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 8000780:	6183      	str	r3, [r0, #24]
  if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
 8000782:	f000 fec7 	bl	8001514 <HAL_TIM_Base_Init>
 8000786:	2800      	cmp	r0, #0
 8000788:	d13e      	bne.n	8000808 <MX_TIM1_Init+0xcc>
  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
 800078a:	2380      	movs	r3, #128	; 0x80
 800078c:	015b      	lsls	r3, r3, #5
 800078e:	9312      	str	r3, [sp, #72]	; 0x48
  if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
 8000790:	a912      	add	r1, sp, #72	; 0x48
 8000792:	4826      	ldr	r0, [pc, #152]	; (800082c <MX_TIM1_Init+0xf0>)
 8000794:	f000 ffda 	bl	800174c <HAL_TIM_ConfigClockSource>
 8000798:	2800      	cmp	r0, #0
 800079a:	d138      	bne.n	800080e <MX_TIM1_Init+0xd2>
  if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
 800079c:	4823      	ldr	r0, [pc, #140]	; (800082c <MX_TIM1_Init+0xf0>)
 800079e:	f000 fee5 	bl	800156c <HAL_TIM_PWM_Init>
 80007a2:	2800      	cmp	r0, #0
 80007a4:	d136      	bne.n	8000814 <MX_TIM1_Init+0xd8>
  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
 80007a6:	2300      	movs	r3, #0
 80007a8:	9310      	str	r3, [sp, #64]	; 0x40
  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
 80007aa:	9311      	str	r3, [sp, #68]	; 0x44
  if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
 80007ac:	a910      	add	r1, sp, #64	; 0x40
 80007ae:	481f      	ldr	r0, [pc, #124]	; (800082c <MX_TIM1_Init+0xf0>)
 80007b0:	f001 f8d0 	bl	8001954 <HAL_TIMEx_MasterConfigSynchronization>
 80007b4:	2800      	cmp	r0, #0
 80007b6:	d130      	bne.n	800081a <MX_TIM1_Init+0xde>
  sConfigOC.OCMode = TIM_OCMODE_PWM1;
 80007b8:	2360      	movs	r3, #96	; 0x60
 80007ba:	9309      	str	r3, [sp, #36]	; 0x24
  sConfigOC.Pulse = 1800;
 80007bc:	23e1      	movs	r3, #225	; 0xe1
 80007be:	00db      	lsls	r3, r3, #3
 80007c0:	930a      	str	r3, [sp, #40]	; 0x28
  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
 80007c2:	2300      	movs	r3, #0
 80007c4:	930b      	str	r3, [sp, #44]	; 0x2c
  sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
 80007c6:	930c      	str	r3, [sp, #48]	; 0x30
  sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;
 80007c8:	2204      	movs	r2, #4
 80007ca:	920d      	str	r2, [sp, #52]	; 0x34
  sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
 80007cc:	930e      	str	r3, [sp, #56]	; 0x38
  sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
 80007ce:	930f      	str	r3, [sp, #60]	; 0x3c
  if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
 80007d0:	2200      	movs	r2, #0
 80007d2:	a909      	add	r1, sp, #36	; 0x24
 80007d4:	4815      	ldr	r0, [pc, #84]	; (800082c <MX_TIM1_Init+0xf0>)
 80007d6:	f000 ff35 	bl	8001644 <HAL_TIM_PWM_ConfigChannel>
 80007da:	2800      	cmp	r0, #0
 80007dc:	d120      	bne.n	8000820 <MX_TIM1_Init+0xe4>
  sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
 80007de:	2300      	movs	r3, #0
 80007e0:	9301      	str	r3, [sp, #4]
  sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
 80007e2:	9302      	str	r3, [sp, #8]
  sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
 80007e4:	9303      	str	r3, [sp, #12]
  sBreakDeadTimeConfig.DeadTime = 0;
 80007e6:	9304      	str	r3, [sp, #16]
  sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
 80007e8:	9305      	str	r3, [sp, #20]
  sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
 80007ea:	2280      	movs	r2, #128	; 0x80
 80007ec:	0192      	lsls	r2, r2, #6
 80007ee:	9206      	str	r2, [sp, #24]
  sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
 80007f0:	9308      	str	r3, [sp, #32]
  if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
 80007f2:	a901      	add	r1, sp, #4
 80007f4:	480d      	ldr	r0, [pc, #52]	; (800082c <MX_TIM1_Init+0xf0>)
 80007f6:	f001 f8db 	bl	80019b0 <HAL_TIMEx_ConfigBreakDeadTime>
 80007fa:	2800      	cmp	r0, #0
 80007fc:	d113      	bne.n	8000826 <MX_TIM1_Init+0xea>
  HAL_TIM_MspPostInit(&htim1);
 80007fe:	480b      	ldr	r0, [pc, #44]	; (800082c <MX_TIM1_Init+0xf0>)
 8000800:	f7ff ff74 	bl	80006ec <HAL_TIM_MspPostInit>
}
 8000804:	b017      	add	sp, #92	; 0x5c
 8000806:	bd00      	pop	{pc}
    Error_Handler();
 8000808:	f7ff fe9c 	bl	8000544 <Error_Handler>
 800080c:	e7bd      	b.n	800078a <MX_TIM1_Init+0x4e>
    Error_Handler();
 800080e:	f7ff fe99 	bl	8000544 <Error_Handler>
 8000812:	e7c3      	b.n	800079c <MX_TIM1_Init+0x60>
    Error_Handler();
 8000814:	f7ff fe96 	bl	8000544 <Error_Handler>
 8000818:	e7c5      	b.n	80007a6 <MX_TIM1_Init+0x6a>
    Error_Handler();
 800081a:	f7ff fe93 	bl	8000544 <Error_Handler>
 800081e:	e7cb      	b.n	80007b8 <MX_TIM1_Init+0x7c>
    Error_Handler();
 8000820:	f7ff fe90 	bl	8000544 <Error_Handler>
 8000824:	e7db      	b.n	80007de <MX_TIM1_Init+0xa2>
    Error_Handler();
 8000826:	f7ff fe8d 	bl	8000544 <Error_Handler>
 800082a:	e7e8      	b.n	80007fe <MX_TIM1_Init+0xc2>
 800082c:	20000098 	.word	0x20000098
 8000830:	40012c00 	.word	0x40012c00

08000834 <Reset_Handler>:

  .section .text.Reset_Handler
  .weak Reset_Handler
  .type Reset_Handler, %function
Reset_Handler:
  ldr   r0, =_estack
 8000834:	480d      	ldr	r0, [pc, #52]	; (800086c <LoopForever+0x2>)
  mov   sp, r0          /* set stack pointer */
 8000836:	4685      	mov	sp, r0

/* Copy the data segment initializers from flash to SRAM */
  ldr r0, =_sdata
 8000838:	480d      	ldr	r0, [pc, #52]	; (8000870 <LoopForever+0x6>)
  ldr r1, =_edata
 800083a:	490e      	ldr	r1, [pc, #56]	; (8000874 <LoopForever+0xa>)
  ldr r2, =_sidata
 800083c:	4a0e      	ldr	r2, [pc, #56]	; (8000878 <LoopForever+0xe>)
  movs r3, #0
 800083e:	2300      	movs	r3, #0
  b LoopCopyDataInit
 8000840:	e002      	b.n	8000848 <LoopCopyDataInit>

08000842 <CopyDataInit>:

CopyDataInit:
  ldr r4, [r2, r3]
 8000842:	58d4      	ldr	r4, [r2, r3]
  str r4, [r0, r3]
 8000844:	50c4      	str	r4, [r0, r3]
  adds r3, r3, #4
 8000846:	3304      	adds	r3, #4

08000848 <LoopCopyDataInit>:

LoopCopyDataInit:
  adds r4, r0, r3
 8000848:	18c4      	adds	r4, r0, r3
  cmp r4, r1
 800084a:	428c      	cmp	r4, r1
  bcc CopyDataInit
 800084c:	d3f9      	bcc.n	8000842 <CopyDataInit>
  
/* Zero fill the bss segment. */
  ldr r2, =_sbss
 800084e:	4a0b      	ldr	r2, [pc, #44]	; (800087c <LoopForever+0x12>)
  ldr r4, =_ebss
 8000850:	4c0b      	ldr	r4, [pc, #44]	; (8000880 <LoopForever+0x16>)
  movs r3, #0
 8000852:	2300      	movs	r3, #0
  b LoopFillZerobss
 8000854:	e001      	b.n	800085a <LoopFillZerobss>

08000856 <FillZerobss>:

FillZerobss:
  str  r3, [r2]
 8000856:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 8000858:	3204      	adds	r2, #4

0800085a <LoopFillZerobss>:

LoopFillZerobss:
  cmp r2, r4
 800085a:	42a2      	cmp	r2, r4
  bcc FillZerobss
 800085c:	d3fb      	bcc.n	8000856 <FillZerobss>

/* Call the clock system intitialization function.*/
  bl  SystemInit
 800085e:	f7ff ff2e 	bl	80006be <SystemInit>
/* Call static constructors */
  bl __libc_init_array
 8000862:	f001 f8db 	bl	8001a1c <__libc_init_array>
/* Call the application's entry point.*/
  bl main
 8000866:	f7ff fe9d 	bl	80005a4 <main>

0800086a <LoopForever>:

LoopForever:
    b LoopForever
 800086a:	e7fe      	b.n	800086a <LoopForever>
  ldr   r0, =_estack
 800086c:	20001000 	.word	0x20001000
  ldr r0, =_sdata
 8000870:	20000000 	.word	0x20000000
  ldr r1, =_edata
 8000874:	20000010 	.word	0x20000010
  ldr r2, =_sidata
 8000878:	08001acc 	.word	0x08001acc
  ldr r2, =_sbss
 800087c:	20000010 	.word	0x20000010
  ldr r4, =_ebss
 8000880:	200000e4 	.word	0x200000e4

08000884 <ADC1_IRQHandler>:
 * @retval : None
*/
    .section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b Infinite_Loop
 8000884:	e7fe      	b.n	8000884 <ADC1_IRQHandler>
	...

08000888 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 8000888:	b510      	push	{r4, lr}
 800088a:	0004      	movs	r4, r0
  /*Configure the SysTick to have interrupt in 1ms time basis*/
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 800088c:	4b0f      	ldr	r3, [pc, #60]	; (80008cc <HAL_InitTick+0x44>)
 800088e:	7819      	ldrb	r1, [r3, #0]
 8000890:	20fa      	movs	r0, #250	; 0xfa
 8000892:	0080      	lsls	r0, r0, #2
 8000894:	f7ff fc38 	bl	8000108 <__udivsi3>
 8000898:	0001      	movs	r1, r0
 800089a:	4b0d      	ldr	r3, [pc, #52]	; (80008d0 <HAL_InitTick+0x48>)
 800089c:	6818      	ldr	r0, [r3, #0]
 800089e:	f7ff fc33 	bl	8000108 <__udivsi3>
 80008a2:	f000 f877 	bl	8000994 <HAL_SYSTICK_Config>
 80008a6:	2800      	cmp	r0, #0
 80008a8:	d10d      	bne.n	80008c6 <HAL_InitTick+0x3e>
  {
    return HAL_ERROR;
  }

  /* Configure the SysTick IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 80008aa:	2c03      	cmp	r4, #3
 80008ac:	d901      	bls.n	80008b2 <HAL_InitTick+0x2a>
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
    uwTickPrio = TickPriority;
  }
  else
  {
    return HAL_ERROR;
 80008ae:	2001      	movs	r0, #1
 80008b0:	e00a      	b.n	80008c8 <HAL_InitTick+0x40>
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 80008b2:	3001      	adds	r0, #1
 80008b4:	2200      	movs	r2, #0
 80008b6:	0021      	movs	r1, r4
 80008b8:	4240      	negs	r0, r0
 80008ba:	f000 f82f 	bl	800091c <HAL_NVIC_SetPriority>
    uwTickPrio = TickPriority;
 80008be:	4b05      	ldr	r3, [pc, #20]	; (80008d4 <HAL_InitTick+0x4c>)
 80008c0:	601c      	str	r4, [r3, #0]
  }

   /* Return function status */
  return HAL_OK;
 80008c2:	2000      	movs	r0, #0
 80008c4:	e000      	b.n	80008c8 <HAL_InitTick+0x40>
    return HAL_ERROR;
 80008c6:	2001      	movs	r0, #1
}
 80008c8:	bd10      	pop	{r4, pc}
 80008ca:	46c0      	nop			; (mov r8, r8)
 80008cc:	20000008 	.word	0x20000008
 80008d0:	20000004 	.word	0x20000004
 80008d4:	2000000c 	.word	0x2000000c

080008d8 <HAL_Init>:
{
 80008d8:	b510      	push	{r4, lr}
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 80008da:	4a06      	ldr	r2, [pc, #24]	; (80008f4 <HAL_Init+0x1c>)
 80008dc:	6813      	ldr	r3, [r2, #0]
 80008de:	2110      	movs	r1, #16
 80008e0:	430b      	orrs	r3, r1
 80008e2:	6013      	str	r3, [r2, #0]
  HAL_InitTick(TICK_INT_PRIORITY);
 80008e4:	2003      	movs	r0, #3
 80008e6:	f7ff ffcf 	bl	8000888 <HAL_InitTick>
  HAL_MspInit();
 80008ea:	f7ff fec3 	bl	8000674 <HAL_MspInit>
}
 80008ee:	2000      	movs	r0, #0
 80008f0:	bd10      	pop	{r4, pc}
 80008f2:	46c0      	nop			; (mov r8, r8)
 80008f4:	40022000 	.word	0x40022000

080008f8 <HAL_IncTick>:
  *       implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
  uwTick += uwTickFreq;
 80008f8:	4a03      	ldr	r2, [pc, #12]	; (8000908 <HAL_IncTick+0x10>)
 80008fa:	6811      	ldr	r1, [r2, #0]
 80008fc:	4b03      	ldr	r3, [pc, #12]	; (800090c <HAL_IncTick+0x14>)
 80008fe:	781b      	ldrb	r3, [r3, #0]
 8000900:	185b      	adds	r3, r3, r1
 8000902:	6013      	str	r3, [r2, #0]
}
 8000904:	4770      	bx	lr
 8000906:	46c0      	nop			; (mov r8, r8)
 8000908:	200000e0 	.word	0x200000e0
 800090c:	20000008 	.word	0x20000008

08000910 <HAL_GetTick>:
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
  return uwTick;
 8000910:	4b01      	ldr	r3, [pc, #4]	; (8000918 <HAL_GetTick+0x8>)
 8000912:	6818      	ldr	r0, [r3, #0]
}
 8000914:	4770      	bx	lr
 8000916:	46c0      	nop			; (mov r8, r8)
 8000918:	200000e0 	.word	0x200000e0

0800091c <HAL_NVIC_SetPriority>:
  *         with stm32f0xx devices, this parameter is a dummy value and it is ignored, because 
  *         no subpriority supported in Cortex M0 based products.   
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{ 
 800091c:	b570      	push	{r4, r5, r6, lr}
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
 800091e:	2800      	cmp	r0, #0
 8000920:	db11      	blt.n	8000946 <HAL_NVIC_SetPriority+0x2a>
  {
    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 8000922:	0883      	lsrs	r3, r0, #2
 8000924:	4e13      	ldr	r6, [pc, #76]	; (8000974 <HAL_NVIC_SetPriority+0x58>)
 8000926:	33c0      	adds	r3, #192	; 0xc0
 8000928:	009b      	lsls	r3, r3, #2
 800092a:	599d      	ldr	r5, [r3, r6]
 800092c:	2403      	movs	r4, #3
 800092e:	4020      	ands	r0, r4
 8000930:	00c0      	lsls	r0, r0, #3
 8000932:	22ff      	movs	r2, #255	; 0xff
 8000934:	0014      	movs	r4, r2
 8000936:	4084      	lsls	r4, r0
 8000938:	43a5      	bics	r5, r4
       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 800093a:	0189      	lsls	r1, r1, #6
 800093c:	400a      	ands	r2, r1
 800093e:	4082      	lsls	r2, r0
    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 8000940:	432a      	orrs	r2, r5
 8000942:	519a      	str	r2, [r3, r6]
  /* Check the parameters */
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
  NVIC_SetPriority(IRQn,PreemptPriority);
}
 8000944:	bd70      	pop	{r4, r5, r6, pc}
  }
  else
  {
    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 8000946:	230f      	movs	r3, #15
 8000948:	4003      	ands	r3, r0
 800094a:	3b08      	subs	r3, #8
 800094c:	089b      	lsrs	r3, r3, #2
 800094e:	3306      	adds	r3, #6
 8000950:	009b      	lsls	r3, r3, #2
 8000952:	4a09      	ldr	r2, [pc, #36]	; (8000978 <HAL_NVIC_SetPriority+0x5c>)
 8000954:	4694      	mov	ip, r2
 8000956:	4463      	add	r3, ip
 8000958:	685c      	ldr	r4, [r3, #4]
 800095a:	2203      	movs	r2, #3
 800095c:	4010      	ands	r0, r2
 800095e:	00c0      	lsls	r0, r0, #3
 8000960:	32fc      	adds	r2, #252	; 0xfc
 8000962:	0015      	movs	r5, r2
 8000964:	4085      	lsls	r5, r0
 8000966:	43ac      	bics	r4, r5
       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
 8000968:	0189      	lsls	r1, r1, #6
 800096a:	400a      	ands	r2, r1
 800096c:	4082      	lsls	r2, r0
    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 800096e:	4322      	orrs	r2, r4
 8000970:	605a      	str	r2, [r3, #4]
 8000972:	e7e7      	b.n	8000944 <HAL_NVIC_SetPriority+0x28>
 8000974:	e000e100 	.word	0xe000e100
 8000978:	e000ed00 	.word	0xe000ed00

0800097c <HAL_NVIC_EnableIRQ>:
  if ((int32_t)(IRQn) >= 0)
 800097c:	2800      	cmp	r0, #0
 800097e:	db05      	blt.n	800098c <HAL_NVIC_EnableIRQ+0x10>
    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 8000980:	231f      	movs	r3, #31
 8000982:	4018      	ands	r0, r3
 8000984:	3b1e      	subs	r3, #30
 8000986:	4083      	lsls	r3, r0
 8000988:	4a01      	ldr	r2, [pc, #4]	; (8000990 <HAL_NVIC_EnableIRQ+0x14>)
 800098a:	6013      	str	r3, [r2, #0]
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
  
  /* Enable interrupt */
  NVIC_EnableIRQ(IRQn);
}
 800098c:	4770      	bx	lr
 800098e:	46c0      	nop			; (mov r8, r8)
 8000990:	e000e100 	.word	0xe000e100

08000994 <HAL_SYSTICK_Config>:
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 8000994:	3801      	subs	r0, #1
 8000996:	2380      	movs	r3, #128	; 0x80
 8000998:	045b      	lsls	r3, r3, #17
 800099a:	4298      	cmp	r0, r3
 800099c:	d20f      	bcs.n	80009be <HAL_SYSTICK_Config+0x2a>
  {
    return (1UL);                                                   /* Reload value impossible */
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 800099e:	4a09      	ldr	r2, [pc, #36]	; (80009c4 <HAL_SYSTICK_Config+0x30>)
 80009a0:	6050      	str	r0, [r2, #4]
    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
 80009a2:	4809      	ldr	r0, [pc, #36]	; (80009c8 <HAL_SYSTICK_Config+0x34>)
 80009a4:	6a03      	ldr	r3, [r0, #32]
 80009a6:	021b      	lsls	r3, r3, #8
 80009a8:	0a1b      	lsrs	r3, r3, #8
 80009aa:	21c0      	movs	r1, #192	; 0xc0
 80009ac:	0609      	lsls	r1, r1, #24
 80009ae:	430b      	orrs	r3, r1
 80009b0:	6203      	str	r3, [r0, #32]
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 80009b2:	2300      	movs	r3, #0
 80009b4:	6093      	str	r3, [r2, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 80009b6:	3307      	adds	r3, #7
 80009b8:	6013      	str	r3, [r2, #0]
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
 80009ba:	2000      	movs	r0, #0
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
   return SysTick_Config(TicksNumb);
}
 80009bc:	4770      	bx	lr
    return (1UL);                                                   /* Reload value impossible */
 80009be:	2001      	movs	r0, #1
   return SysTick_Config(TicksNumb);
 80009c0:	e7fc      	b.n	80009bc <HAL_SYSTICK_Config+0x28>
 80009c2:	46c0      	nop			; (mov r8, r8)
 80009c4:	e000e010 	.word	0xe000e010
 80009c8:	e000ed00 	.word	0xe000ed00

080009cc <HAL_GPIO_Init>:
  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 80009cc:	b5f0      	push	{r4, r5, r6, r7, lr}
 80009ce:	b083      	sub	sp, #12
  uint32_t position = 0x00u;
 80009d0:	2300      	movs	r3, #0
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 80009d2:	e057      	b.n	8000a84 <HAL_GPIO_Init+0xb8>
         ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
      {
        /* Check the Speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
        /* Configure the IO Speed */
        temp = GPIOx->OSPEEDR;
 80009d4:	6884      	ldr	r4, [r0, #8]
        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u));
 80009d6:	005f      	lsls	r7, r3, #1
 80009d8:	2603      	movs	r6, #3
 80009da:	40be      	lsls	r6, r7
 80009dc:	43b4      	bics	r4, r6
 80009de:	0026      	movs	r6, r4
        temp |= (GPIO_Init->Speed << (position * 2u));
 80009e0:	68cc      	ldr	r4, [r1, #12]
 80009e2:	40bc      	lsls	r4, r7
 80009e4:	4334      	orrs	r4, r6
        GPIOx->OSPEEDR = temp;
 80009e6:	6084      	str	r4, [r0, #8]

        /* Configure the IO Output Type */
        temp = GPIOx->OTYPER;
 80009e8:	6844      	ldr	r4, [r0, #4]
        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
 80009ea:	4394      	bics	r4, r2
        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
 80009ec:	684a      	ldr	r2, [r1, #4]
 80009ee:	0916      	lsrs	r6, r2, #4
 80009f0:	2201      	movs	r2, #1
 80009f2:	4032      	ands	r2, r6
 80009f4:	409a      	lsls	r2, r3
 80009f6:	4322      	orrs	r2, r4
        GPIOx->OTYPER = temp;
 80009f8:	6042      	str	r2, [r0, #4]
 80009fa:	e053      	b.n	8000aa4 <HAL_GPIO_Init+0xd8>
        /* Check the Alternate function parameters */
        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));

        /* Configure Alternate function mapped with the current IO */
        temp = GPIOx->AFR[position >> 3u];
 80009fc:	08dc      	lsrs	r4, r3, #3
 80009fe:	3408      	adds	r4, #8
 8000a00:	00a4      	lsls	r4, r4, #2
 8000a02:	5826      	ldr	r6, [r4, r0]
        temp &= ~(0xFu << ((position & 0x07u) * 4u));
 8000a04:	3205      	adds	r2, #5
 8000a06:	401a      	ands	r2, r3
 8000a08:	0092      	lsls	r2, r2, #2
 8000a0a:	270f      	movs	r7, #15
 8000a0c:	4097      	lsls	r7, r2
 8000a0e:	43be      	bics	r6, r7
        temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
 8000a10:	690f      	ldr	r7, [r1, #16]
 8000a12:	4097      	lsls	r7, r2
 8000a14:	003a      	movs	r2, r7
 8000a16:	4332      	orrs	r2, r6
        GPIOx->AFR[position >> 3u] = temp;
 8000a18:	5022      	str	r2, [r4, r0]
 8000a1a:	e057      	b.n	8000acc <HAL_GPIO_Init+0x100>
        /* Enable SYSCFG Clock */
        __HAL_RCC_SYSCFG_CLK_ENABLE();

        temp = SYSCFG->EXTICR[position >> 2u];
        temp &= ~(0x0FuL << (4u * (position & 0x03u)));
        temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
 8000a1c:	2603      	movs	r6, #3
 8000a1e:	e000      	b.n	8000a22 <HAL_GPIO_Init+0x56>
 8000a20:	2600      	movs	r6, #0
 8000a22:	40a6      	lsls	r6, r4
 8000a24:	0034      	movs	r4, r6
 8000a26:	433c      	orrs	r4, r7
        SYSCFG->EXTICR[position >> 2u] = temp;
 8000a28:	3202      	adds	r2, #2
 8000a2a:	0092      	lsls	r2, r2, #2
 8000a2c:	4e44      	ldr	r6, [pc, #272]	; (8000b40 <HAL_GPIO_Init+0x174>)
 8000a2e:	5194      	str	r4, [r2, r6]

        /* Clear EXTI line configuration */
        temp = EXTI->IMR;
 8000a30:	4a44      	ldr	r2, [pc, #272]	; (8000b44 <HAL_GPIO_Init+0x178>)
 8000a32:	6814      	ldr	r4, [r2, #0]
        temp &= ~(iocurrent);
 8000a34:	43ea      	mvns	r2, r5
 8000a36:	0026      	movs	r6, r4
 8000a38:	43ae      	bics	r6, r5
        if((GPIO_Init->Mode & EXTI_IT) != 0x00u)
 8000a3a:	684f      	ldr	r7, [r1, #4]
 8000a3c:	03ff      	lsls	r7, r7, #15
 8000a3e:	d501      	bpl.n	8000a44 <HAL_GPIO_Init+0x78>
        {
          temp |= iocurrent;
 8000a40:	432c      	orrs	r4, r5
 8000a42:	0026      	movs	r6, r4
        }
        EXTI->IMR = temp;
 8000a44:	4c3f      	ldr	r4, [pc, #252]	; (8000b44 <HAL_GPIO_Init+0x178>)
 8000a46:	6026      	str	r6, [r4, #0]

        temp = EXTI->EMR;
 8000a48:	6864      	ldr	r4, [r4, #4]
        temp &= ~(iocurrent);
 8000a4a:	0026      	movs	r6, r4
 8000a4c:	4016      	ands	r6, r2
        if((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
 8000a4e:	684f      	ldr	r7, [r1, #4]
 8000a50:	03bf      	lsls	r7, r7, #14
 8000a52:	d501      	bpl.n	8000a58 <HAL_GPIO_Init+0x8c>
        {
          temp |= iocurrent;
 8000a54:	432c      	orrs	r4, r5
 8000a56:	0026      	movs	r6, r4
        }
        EXTI->EMR = temp;
 8000a58:	4c3a      	ldr	r4, [pc, #232]	; (8000b44 <HAL_GPIO_Init+0x178>)
 8000a5a:	6066      	str	r6, [r4, #4]

        /* Clear Rising Falling edge configuration */
        temp = EXTI->RTSR;
 8000a5c:	68a4      	ldr	r4, [r4, #8]
        temp &= ~(iocurrent);
 8000a5e:	0026      	movs	r6, r4
 8000a60:	4016      	ands	r6, r2
        if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
 8000a62:	684f      	ldr	r7, [r1, #4]
 8000a64:	02ff      	lsls	r7, r7, #11
 8000a66:	d501      	bpl.n	8000a6c <HAL_GPIO_Init+0xa0>
        {
          temp |= iocurrent;
 8000a68:	432c      	orrs	r4, r5
 8000a6a:	0026      	movs	r6, r4
        }
        EXTI->RTSR = temp;
 8000a6c:	4c35      	ldr	r4, [pc, #212]	; (8000b44 <HAL_GPIO_Init+0x178>)
 8000a6e:	60a6      	str	r6, [r4, #8]

        temp = EXTI->FTSR;
 8000a70:	68e4      	ldr	r4, [r4, #12]
        temp &= ~(iocurrent);
 8000a72:	4022      	ands	r2, r4
        if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
 8000a74:	684e      	ldr	r6, [r1, #4]
 8000a76:	02b6      	lsls	r6, r6, #10
 8000a78:	d501      	bpl.n	8000a7e <HAL_GPIO_Init+0xb2>
        {
          temp |= iocurrent;
 8000a7a:	002a      	movs	r2, r5
 8000a7c:	4322      	orrs	r2, r4
        }
        EXTI->FTSR = temp;
 8000a7e:	4c31      	ldr	r4, [pc, #196]	; (8000b44 <HAL_GPIO_Init+0x178>)
 8000a80:	60e2      	str	r2, [r4, #12]
      }
    }

    position++;
 8000a82:	3301      	adds	r3, #1
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 8000a84:	680c      	ldr	r4, [r1, #0]
 8000a86:	0022      	movs	r2, r4
 8000a88:	40da      	lsrs	r2, r3
 8000a8a:	d057      	beq.n	8000b3c <HAL_GPIO_Init+0x170>
    iocurrent = (GPIO_Init->Pin) & (1uL << position);
 8000a8c:	2201      	movs	r2, #1
 8000a8e:	409a      	lsls	r2, r3
 8000a90:	0025      	movs	r5, r4
 8000a92:	4015      	ands	r5, r2
    if (iocurrent != 0x00u)
 8000a94:	4214      	tst	r4, r2
 8000a96:	d0f4      	beq.n	8000a82 <HAL_GPIO_Init+0xb6>
      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
 8000a98:	2403      	movs	r4, #3
 8000a9a:	684e      	ldr	r6, [r1, #4]
 8000a9c:	4034      	ands	r4, r6
 8000a9e:	3c01      	subs	r4, #1
 8000aa0:	2c01      	cmp	r4, #1
 8000aa2:	d997      	bls.n	80009d4 <HAL_GPIO_Init+0x8>
      if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
 8000aa4:	2203      	movs	r2, #3
 8000aa6:	684c      	ldr	r4, [r1, #4]
 8000aa8:	4022      	ands	r2, r4
 8000aaa:	2a03      	cmp	r2, #3
 8000aac:	d009      	beq.n	8000ac2 <HAL_GPIO_Init+0xf6>
        temp = GPIOx->PUPDR;
 8000aae:	68c2      	ldr	r2, [r0, #12]
        temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u));
 8000ab0:	005e      	lsls	r6, r3, #1
 8000ab2:	2403      	movs	r4, #3
 8000ab4:	40b4      	lsls	r4, r6
 8000ab6:	43a2      	bics	r2, r4
 8000ab8:	0014      	movs	r4, r2
        temp |= ((GPIO_Init->Pull) << (position * 2u));
 8000aba:	688a      	ldr	r2, [r1, #8]
 8000abc:	40b2      	lsls	r2, r6
 8000abe:	4322      	orrs	r2, r4
        GPIOx->PUPDR = temp;
 8000ac0:	60c2      	str	r2, [r0, #12]
      if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 8000ac2:	2203      	movs	r2, #3
 8000ac4:	684c      	ldr	r4, [r1, #4]
 8000ac6:	4022      	ands	r2, r4
 8000ac8:	2a02      	cmp	r2, #2
 8000aca:	d097      	beq.n	80009fc <HAL_GPIO_Init+0x30>
      temp = GPIOx->MODER;
 8000acc:	6804      	ldr	r4, [r0, #0]
      temp &= ~(GPIO_MODER_MODER0 << (position * 2u));
 8000ace:	005e      	lsls	r6, r3, #1
 8000ad0:	2203      	movs	r2, #3
 8000ad2:	0017      	movs	r7, r2
 8000ad4:	40b7      	lsls	r7, r6
 8000ad6:	43bc      	bics	r4, r7
      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
 8000ad8:	684f      	ldr	r7, [r1, #4]
 8000ada:	403a      	ands	r2, r7
 8000adc:	40b2      	lsls	r2, r6
 8000ade:	4322      	orrs	r2, r4
      GPIOx->MODER = temp;
 8000ae0:	6002      	str	r2, [r0, #0]
      if((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
 8000ae2:	22c0      	movs	r2, #192	; 0xc0
 8000ae4:	0292      	lsls	r2, r2, #10
 8000ae6:	684c      	ldr	r4, [r1, #4]
 8000ae8:	4214      	tst	r4, r2
 8000aea:	d0ca      	beq.n	8000a82 <HAL_GPIO_Init+0xb6>
        __HAL_RCC_SYSCFG_CLK_ENABLE();
 8000aec:	4c16      	ldr	r4, [pc, #88]	; (8000b48 <HAL_GPIO_Init+0x17c>)
 8000aee:	69a6      	ldr	r6, [r4, #24]
 8000af0:	2201      	movs	r2, #1
 8000af2:	4316      	orrs	r6, r2
 8000af4:	61a6      	str	r6, [r4, #24]
 8000af6:	69a4      	ldr	r4, [r4, #24]
 8000af8:	4022      	ands	r2, r4
 8000afa:	9201      	str	r2, [sp, #4]
 8000afc:	9a01      	ldr	r2, [sp, #4]
        temp = SYSCFG->EXTICR[position >> 2u];
 8000afe:	089a      	lsrs	r2, r3, #2
 8000b00:	1c94      	adds	r4, r2, #2
 8000b02:	00a4      	lsls	r4, r4, #2
 8000b04:	4e0e      	ldr	r6, [pc, #56]	; (8000b40 <HAL_GPIO_Init+0x174>)
 8000b06:	59a7      	ldr	r7, [r4, r6]
        temp &= ~(0x0FuL << (4u * (position & 0x03u)));
 8000b08:	2403      	movs	r4, #3
 8000b0a:	401c      	ands	r4, r3
 8000b0c:	00a4      	lsls	r4, r4, #2
 8000b0e:	260f      	movs	r6, #15
 8000b10:	40a6      	lsls	r6, r4
 8000b12:	43b7      	bics	r7, r6
        temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
 8000b14:	2690      	movs	r6, #144	; 0x90
 8000b16:	05f6      	lsls	r6, r6, #23
 8000b18:	42b0      	cmp	r0, r6
 8000b1a:	d081      	beq.n	8000a20 <HAL_GPIO_Init+0x54>
 8000b1c:	4e0b      	ldr	r6, [pc, #44]	; (8000b4c <HAL_GPIO_Init+0x180>)
 8000b1e:	42b0      	cmp	r0, r6
 8000b20:	d008      	beq.n	8000b34 <HAL_GPIO_Init+0x168>
 8000b22:	4e0b      	ldr	r6, [pc, #44]	; (8000b50 <HAL_GPIO_Init+0x184>)
 8000b24:	42b0      	cmp	r0, r6
 8000b26:	d007      	beq.n	8000b38 <HAL_GPIO_Init+0x16c>
 8000b28:	4e0a      	ldr	r6, [pc, #40]	; (8000b54 <HAL_GPIO_Init+0x188>)
 8000b2a:	42b0      	cmp	r0, r6
 8000b2c:	d100      	bne.n	8000b30 <HAL_GPIO_Init+0x164>
 8000b2e:	e775      	b.n	8000a1c <HAL_GPIO_Init+0x50>
 8000b30:	2605      	movs	r6, #5
 8000b32:	e776      	b.n	8000a22 <HAL_GPIO_Init+0x56>
 8000b34:	2601      	movs	r6, #1
 8000b36:	e774      	b.n	8000a22 <HAL_GPIO_Init+0x56>
 8000b38:	2602      	movs	r6, #2
 8000b3a:	e772      	b.n	8000a22 <HAL_GPIO_Init+0x56>
  } 
}
 8000b3c:	b003      	add	sp, #12
 8000b3e:	bdf0      	pop	{r4, r5, r6, r7, pc}
 8000b40:	40010000 	.word	0x40010000
 8000b44:	40010400 	.word	0x40010400
 8000b48:	40021000 	.word	0x40021000
 8000b4c:	48000400 	.word	0x48000400
 8000b50:	48000800 	.word	0x48000800
 8000b54:	48000c00 	.word	0x48000c00

08000b58 <HAL_GPIO_WritePin>:
{
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if (PinState != GPIO_PIN_RESET)
 8000b58:	2a00      	cmp	r2, #0
 8000b5a:	d001      	beq.n	8000b60 <HAL_GPIO_WritePin+0x8>
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin;
 8000b5c:	6181      	str	r1, [r0, #24]
  }
  else
  {
    GPIOx->BRR = (uint32_t)GPIO_Pin;
  }
}
 8000b5e:	4770      	bx	lr
    GPIOx->BRR = (uint32_t)GPIO_Pin;
 8000b60:	6281      	str	r1, [r0, #40]	; 0x28
}
 8000b62:	e7fc      	b.n	8000b5e <HAL_GPIO_WritePin+0x6>

08000b64 <HAL_GPIO_EXTI_Callback>:
  UNUSED(GPIO_Pin);

  /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_GPIO_EXTI_Callback could be implemented in the user file
   */ 
}
 8000b64:	4770      	bx	lr
	...

08000b68 <HAL_GPIO_EXTI_IRQHandler>:
{
 8000b68:	b510      	push	{r4, lr}
  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != 0x00u)
 8000b6a:	4b05      	ldr	r3, [pc, #20]	; (8000b80 <HAL_GPIO_EXTI_IRQHandler+0x18>)
 8000b6c:	695b      	ldr	r3, [r3, #20]
 8000b6e:	4218      	tst	r0, r3
 8000b70:	d100      	bne.n	8000b74 <HAL_GPIO_EXTI_IRQHandler+0xc>
}
 8000b72:	bd10      	pop	{r4, pc}
    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
 8000b74:	4b02      	ldr	r3, [pc, #8]	; (8000b80 <HAL_GPIO_EXTI_IRQHandler+0x18>)
 8000b76:	6158      	str	r0, [r3, #20]
    HAL_GPIO_EXTI_Callback(GPIO_Pin);
 8000b78:	f7ff fff4 	bl	8000b64 <HAL_GPIO_EXTI_Callback>
}
 8000b7c:	e7f9      	b.n	8000b72 <HAL_GPIO_EXTI_IRQHandler+0xa>
 8000b7e:	46c0      	nop			; (mov r8, r8)
 8000b80:	40010400 	.word	0x40010400

08000b84 <HAL_RCC_OscConfig>:
  *         supported by this macro. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 8000b84:	b570      	push	{r4, r5, r6, lr}
 8000b86:	b082      	sub	sp, #8
 8000b88:	1e04      	subs	r4, r0, #0
  uint32_t tickstart;
  uint32_t pll_config;
  uint32_t pll_config2;

  /* Check Null pointer */
  if(RCC_OscInitStruct == NULL)
 8000b8a:	d100      	bne.n	8000b8e <HAL_RCC_OscConfig+0xa>
 8000b8c:	e22e      	b.n	8000fec <HAL_RCC_OscConfig+0x468>

  /* Check the parameters */
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));

  /*------------------------------- HSE Configuration ------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8000b8e:	6803      	ldr	r3, [r0, #0]
 8000b90:	07db      	lsls	r3, r3, #31
 8000b92:	d526      	bpl.n	8000be2 <HAL_RCC_OscConfig+0x5e>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) 
 8000b94:	4bae      	ldr	r3, [pc, #696]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000b96:	685a      	ldr	r2, [r3, #4]
 8000b98:	230c      	movs	r3, #12
 8000b9a:	4013      	ands	r3, r2
 8000b9c:	2b04      	cmp	r3, #4
 8000b9e:	d018      	beq.n	8000bd2 <HAL_RCC_OscConfig+0x4e>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
 8000ba0:	4bab      	ldr	r3, [pc, #684]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000ba2:	685a      	ldr	r2, [r3, #4]
 8000ba4:	230c      	movs	r3, #12
 8000ba6:	4013      	ands	r3, r2
 8000ba8:	2b08      	cmp	r3, #8
 8000baa:	d00e      	beq.n	8000bca <HAL_RCC_OscConfig+0x46>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8000bac:	6863      	ldr	r3, [r4, #4]
 8000bae:	2b01      	cmp	r3, #1
 8000bb0:	d03c      	beq.n	8000c2c <HAL_RCC_OscConfig+0xa8>
 8000bb2:	2b00      	cmp	r3, #0
 8000bb4:	d151      	bne.n	8000c5a <HAL_RCC_OscConfig+0xd6>
 8000bb6:	4ba6      	ldr	r3, [pc, #664]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000bb8:	681a      	ldr	r2, [r3, #0]
 8000bba:	49a6      	ldr	r1, [pc, #664]	; (8000e54 <HAL_RCC_OscConfig+0x2d0>)
 8000bbc:	400a      	ands	r2, r1
 8000bbe:	601a      	str	r2, [r3, #0]
 8000bc0:	681a      	ldr	r2, [r3, #0]
 8000bc2:	49a5      	ldr	r1, [pc, #660]	; (8000e58 <HAL_RCC_OscConfig+0x2d4>)
 8000bc4:	400a      	ands	r2, r1
 8000bc6:	601a      	str	r2, [r3, #0]
 8000bc8:	e036      	b.n	8000c38 <HAL_RCC_OscConfig+0xb4>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
 8000bca:	4ba1      	ldr	r3, [pc, #644]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000bcc:	685b      	ldr	r3, [r3, #4]
 8000bce:	03db      	lsls	r3, r3, #15
 8000bd0:	d5ec      	bpl.n	8000bac <HAL_RCC_OscConfig+0x28>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8000bd2:	4b9f      	ldr	r3, [pc, #636]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000bd4:	681b      	ldr	r3, [r3, #0]
 8000bd6:	039b      	lsls	r3, r3, #14
 8000bd8:	d503      	bpl.n	8000be2 <HAL_RCC_OscConfig+0x5e>
 8000bda:	6863      	ldr	r3, [r4, #4]
 8000bdc:	2b00      	cmp	r3, #0
 8000bde:	d100      	bne.n	8000be2 <HAL_RCC_OscConfig+0x5e>
 8000be0:	e207      	b.n	8000ff2 <HAL_RCC_OscConfig+0x46e>
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8000be2:	6823      	ldr	r3, [r4, #0]
 8000be4:	079b      	lsls	r3, r3, #30
 8000be6:	d572      	bpl.n	8000cce <HAL_RCC_OscConfig+0x14a>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
    
    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ 
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) 
 8000be8:	4b99      	ldr	r3, [pc, #612]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000bea:	685b      	ldr	r3, [r3, #4]
 8000bec:	220c      	movs	r2, #12
 8000bee:	421a      	tst	r2, r3
 8000bf0:	d05d      	beq.n	8000cae <HAL_RCC_OscConfig+0x12a>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
 8000bf2:	4b97      	ldr	r3, [pc, #604]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000bf4:	685a      	ldr	r2, [r3, #4]
 8000bf6:	230c      	movs	r3, #12
 8000bf8:	4013      	ands	r3, r2
 8000bfa:	2b08      	cmp	r3, #8
 8000bfc:	d053      	beq.n	8000ca6 <HAL_RCC_OscConfig+0x122>
      }
    }
    else
    {
      /* Check the HSI State */
      if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 8000bfe:	68e3      	ldr	r3, [r4, #12]
 8000c00:	2b00      	cmp	r3, #0
 8000c02:	d100      	bne.n	8000c06 <HAL_RCC_OscConfig+0x82>
 8000c04:	e085      	b.n	8000d12 <HAL_RCC_OscConfig+0x18e>
      {
       /* Enable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_ENABLE();
 8000c06:	4a92      	ldr	r2, [pc, #584]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000c08:	6813      	ldr	r3, [r2, #0]
 8000c0a:	2101      	movs	r1, #1
 8000c0c:	430b      	orrs	r3, r1
 8000c0e:	6013      	str	r3, [r2, #0]
        
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000c10:	f7ff fe7e 	bl	8000910 <HAL_GetTick>
 8000c14:	0005      	movs	r5, r0
        
        /* Wait till HSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8000c16:	4b8e      	ldr	r3, [pc, #568]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000c18:	681b      	ldr	r3, [r3, #0]
 8000c1a:	079b      	lsls	r3, r3, #30
 8000c1c:	d470      	bmi.n	8000d00 <HAL_RCC_OscConfig+0x17c>
        {
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8000c1e:	f7ff fe77 	bl	8000910 <HAL_GetTick>
 8000c22:	1b40      	subs	r0, r0, r5
 8000c24:	2802      	cmp	r0, #2
 8000c26:	d9f6      	bls.n	8000c16 <HAL_RCC_OscConfig+0x92>
          {
            return HAL_TIMEOUT;
 8000c28:	2003      	movs	r0, #3
 8000c2a:	e1e0      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8000c2c:	4a88      	ldr	r2, [pc, #544]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000c2e:	6811      	ldr	r1, [r2, #0]
 8000c30:	2380      	movs	r3, #128	; 0x80
 8000c32:	025b      	lsls	r3, r3, #9
 8000c34:	430b      	orrs	r3, r1
 8000c36:	6013      	str	r3, [r2, #0]
      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 8000c38:	6863      	ldr	r3, [r4, #4]
 8000c3a:	2b00      	cmp	r3, #0
 8000c3c:	d025      	beq.n	8000c8a <HAL_RCC_OscConfig+0x106>
        tickstart = HAL_GetTick();
 8000c3e:	f7ff fe67 	bl	8000910 <HAL_GetTick>
 8000c42:	0005      	movs	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8000c44:	4b82      	ldr	r3, [pc, #520]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000c46:	681b      	ldr	r3, [r3, #0]
 8000c48:	039b      	lsls	r3, r3, #14
 8000c4a:	d4ca      	bmi.n	8000be2 <HAL_RCC_OscConfig+0x5e>
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8000c4c:	f7ff fe60 	bl	8000910 <HAL_GetTick>
 8000c50:	1b40      	subs	r0, r0, r5
 8000c52:	2864      	cmp	r0, #100	; 0x64
 8000c54:	d9f6      	bls.n	8000c44 <HAL_RCC_OscConfig+0xc0>
            return HAL_TIMEOUT;
 8000c56:	2003      	movs	r0, #3
 8000c58:	e1c9      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8000c5a:	2b05      	cmp	r3, #5
 8000c5c:	d009      	beq.n	8000c72 <HAL_RCC_OscConfig+0xee>
 8000c5e:	4b7c      	ldr	r3, [pc, #496]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000c60:	681a      	ldr	r2, [r3, #0]
 8000c62:	497c      	ldr	r1, [pc, #496]	; (8000e54 <HAL_RCC_OscConfig+0x2d0>)
 8000c64:	400a      	ands	r2, r1
 8000c66:	601a      	str	r2, [r3, #0]
 8000c68:	681a      	ldr	r2, [r3, #0]
 8000c6a:	497b      	ldr	r1, [pc, #492]	; (8000e58 <HAL_RCC_OscConfig+0x2d4>)
 8000c6c:	400a      	ands	r2, r1
 8000c6e:	601a      	str	r2, [r3, #0]
 8000c70:	e7e2      	b.n	8000c38 <HAL_RCC_OscConfig+0xb4>
 8000c72:	4b77      	ldr	r3, [pc, #476]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000c74:	6819      	ldr	r1, [r3, #0]
 8000c76:	2280      	movs	r2, #128	; 0x80
 8000c78:	02d2      	lsls	r2, r2, #11
 8000c7a:	430a      	orrs	r2, r1
 8000c7c:	601a      	str	r2, [r3, #0]
 8000c7e:	6819      	ldr	r1, [r3, #0]
 8000c80:	2280      	movs	r2, #128	; 0x80
 8000c82:	0252      	lsls	r2, r2, #9
 8000c84:	430a      	orrs	r2, r1
 8000c86:	601a      	str	r2, [r3, #0]
 8000c88:	e7d6      	b.n	8000c38 <HAL_RCC_OscConfig+0xb4>
        tickstart = HAL_GetTick();
 8000c8a:	f7ff fe41 	bl	8000910 <HAL_GetTick>
 8000c8e:	0005      	movs	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 8000c90:	4b6f      	ldr	r3, [pc, #444]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000c92:	681b      	ldr	r3, [r3, #0]
 8000c94:	039b      	lsls	r3, r3, #14
 8000c96:	d5a4      	bpl.n	8000be2 <HAL_RCC_OscConfig+0x5e>
           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8000c98:	f7ff fe3a 	bl	8000910 <HAL_GetTick>
 8000c9c:	1b40      	subs	r0, r0, r5
 8000c9e:	2864      	cmp	r0, #100	; 0x64
 8000ca0:	d9f6      	bls.n	8000c90 <HAL_RCC_OscConfig+0x10c>
            return HAL_TIMEOUT;
 8000ca2:	2003      	movs	r0, #3
 8000ca4:	e1a3      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
 8000ca6:	4b6a      	ldr	r3, [pc, #424]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000ca8:	685b      	ldr	r3, [r3, #4]
 8000caa:	03db      	lsls	r3, r3, #15
 8000cac:	d4a7      	bmi.n	8000bfe <HAL_RCC_OscConfig+0x7a>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8000cae:	4b68      	ldr	r3, [pc, #416]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000cb0:	681b      	ldr	r3, [r3, #0]
 8000cb2:	079b      	lsls	r3, r3, #30
 8000cb4:	d503      	bpl.n	8000cbe <HAL_RCC_OscConfig+0x13a>
 8000cb6:	68e3      	ldr	r3, [r4, #12]
 8000cb8:	2b01      	cmp	r3, #1
 8000cba:	d000      	beq.n	8000cbe <HAL_RCC_OscConfig+0x13a>
 8000cbc:	e19b      	b.n	8000ff6 <HAL_RCC_OscConfig+0x472>
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8000cbe:	4964      	ldr	r1, [pc, #400]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000cc0:	680b      	ldr	r3, [r1, #0]
 8000cc2:	22f8      	movs	r2, #248	; 0xf8
 8000cc4:	4393      	bics	r3, r2
 8000cc6:	6922      	ldr	r2, [r4, #16]
 8000cc8:	00d2      	lsls	r2, r2, #3
 8000cca:	4313      	orrs	r3, r2
 8000ccc:	600b      	str	r3, [r1, #0]
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8000cce:	6823      	ldr	r3, [r4, #0]
 8000cd0:	071b      	lsls	r3, r3, #28
 8000cd2:	d544      	bpl.n	8000d5e <HAL_RCC_OscConfig+0x1da>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
    
    /* Check the LSI State */
    if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 8000cd4:	69e3      	ldr	r3, [r4, #28]
 8000cd6:	2b00      	cmp	r3, #0
 8000cd8:	d02e      	beq.n	8000d38 <HAL_RCC_OscConfig+0x1b4>
    {
      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 8000cda:	4a5d      	ldr	r2, [pc, #372]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000cdc:	6a53      	ldr	r3, [r2, #36]	; 0x24
 8000cde:	2101      	movs	r1, #1
 8000ce0:	430b      	orrs	r3, r1
 8000ce2:	6253      	str	r3, [r2, #36]	; 0x24
      
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8000ce4:	f7ff fe14 	bl	8000910 <HAL_GetTick>
 8000ce8:	0005      	movs	r5, r0
      
      /* Wait till LSI is ready */  
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 8000cea:	4b59      	ldr	r3, [pc, #356]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000cec:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8000cee:	079b      	lsls	r3, r3, #30
 8000cf0:	d435      	bmi.n	8000d5e <HAL_RCC_OscConfig+0x1da>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8000cf2:	f7ff fe0d 	bl	8000910 <HAL_GetTick>
 8000cf6:	1b40      	subs	r0, r0, r5
 8000cf8:	2802      	cmp	r0, #2
 8000cfa:	d9f6      	bls.n	8000cea <HAL_RCC_OscConfig+0x166>
        {
          return HAL_TIMEOUT;
 8000cfc:	2003      	movs	r0, #3
 8000cfe:	e176      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8000d00:	4953      	ldr	r1, [pc, #332]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000d02:	680b      	ldr	r3, [r1, #0]
 8000d04:	22f8      	movs	r2, #248	; 0xf8
 8000d06:	4393      	bics	r3, r2
 8000d08:	6922      	ldr	r2, [r4, #16]
 8000d0a:	00d2      	lsls	r2, r2, #3
 8000d0c:	4313      	orrs	r3, r2
 8000d0e:	600b      	str	r3, [r1, #0]
 8000d10:	e7dd      	b.n	8000cce <HAL_RCC_OscConfig+0x14a>
        __HAL_RCC_HSI_DISABLE();
 8000d12:	4a4f      	ldr	r2, [pc, #316]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000d14:	6813      	ldr	r3, [r2, #0]
 8000d16:	2101      	movs	r1, #1
 8000d18:	438b      	bics	r3, r1
 8000d1a:	6013      	str	r3, [r2, #0]
        tickstart = HAL_GetTick();
 8000d1c:	f7ff fdf8 	bl	8000910 <HAL_GetTick>
 8000d20:	0005      	movs	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 8000d22:	4b4b      	ldr	r3, [pc, #300]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000d24:	681b      	ldr	r3, [r3, #0]
 8000d26:	079b      	lsls	r3, r3, #30
 8000d28:	d5d1      	bpl.n	8000cce <HAL_RCC_OscConfig+0x14a>
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8000d2a:	f7ff fdf1 	bl	8000910 <HAL_GetTick>
 8000d2e:	1b40      	subs	r0, r0, r5
 8000d30:	2802      	cmp	r0, #2
 8000d32:	d9f6      	bls.n	8000d22 <HAL_RCC_OscConfig+0x19e>
            return HAL_TIMEOUT;
 8000d34:	2003      	movs	r0, #3
 8000d36:	e15a      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 8000d38:	4a45      	ldr	r2, [pc, #276]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000d3a:	6a53      	ldr	r3, [r2, #36]	; 0x24
 8000d3c:	2101      	movs	r1, #1
 8000d3e:	438b      	bics	r3, r1
 8000d40:	6253      	str	r3, [r2, #36]	; 0x24
      
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8000d42:	f7ff fde5 	bl	8000910 <HAL_GetTick>
 8000d46:	0005      	movs	r5, r0
      
      /* Wait till LSI is disabled */  
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 8000d48:	4b41      	ldr	r3, [pc, #260]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000d4a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8000d4c:	079b      	lsls	r3, r3, #30
 8000d4e:	d506      	bpl.n	8000d5e <HAL_RCC_OscConfig+0x1da>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8000d50:	f7ff fdde 	bl	8000910 <HAL_GetTick>
 8000d54:	1b40      	subs	r0, r0, r5
 8000d56:	2802      	cmp	r0, #2
 8000d58:	d9f6      	bls.n	8000d48 <HAL_RCC_OscConfig+0x1c4>
        {
          return HAL_TIMEOUT;
 8000d5a:	2003      	movs	r0, #3
 8000d5c:	e147      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/ 
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8000d5e:	6823      	ldr	r3, [r4, #0]
 8000d60:	075b      	lsls	r3, r3, #29
 8000d62:	d400      	bmi.n	8000d66 <HAL_RCC_OscConfig+0x1e2>
 8000d64:	e080      	b.n	8000e68 <HAL_RCC_OscConfig+0x2e4>
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */
    /* Requires to enable write access to Backup Domain of necessary */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 8000d66:	4b3a      	ldr	r3, [pc, #232]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000d68:	69db      	ldr	r3, [r3, #28]
 8000d6a:	00db      	lsls	r3, r3, #3
 8000d6c:	d41d      	bmi.n	8000daa <HAL_RCC_OscConfig+0x226>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8000d6e:	4a38      	ldr	r2, [pc, #224]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000d70:	69d1      	ldr	r1, [r2, #28]
 8000d72:	2080      	movs	r0, #128	; 0x80
 8000d74:	0540      	lsls	r0, r0, #21
 8000d76:	4301      	orrs	r1, r0
 8000d78:	61d1      	str	r1, [r2, #28]
 8000d7a:	69d3      	ldr	r3, [r2, #28]
 8000d7c:	4003      	ands	r3, r0
 8000d7e:	9301      	str	r3, [sp, #4]
 8000d80:	9b01      	ldr	r3, [sp, #4]
      pwrclkchanged = SET;
 8000d82:	2501      	movs	r5, #1
    }
    
    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8000d84:	4b35      	ldr	r3, [pc, #212]	; (8000e5c <HAL_RCC_OscConfig+0x2d8>)
 8000d86:	681b      	ldr	r3, [r3, #0]
 8000d88:	05db      	lsls	r3, r3, #23
 8000d8a:	d510      	bpl.n	8000dae <HAL_RCC_OscConfig+0x22a>
        }
      }
    }

    /* Set the new LSE configuration -----------------------------------------*/
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8000d8c:	68a3      	ldr	r3, [r4, #8]
 8000d8e:	2b01      	cmp	r3, #1
 8000d90:	d021      	beq.n	8000dd6 <HAL_RCC_OscConfig+0x252>
 8000d92:	2b00      	cmp	r3, #0
 8000d94:	d136      	bne.n	8000e04 <HAL_RCC_OscConfig+0x280>
 8000d96:	4b2e      	ldr	r3, [pc, #184]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000d98:	6a1a      	ldr	r2, [r3, #32]
 8000d9a:	2101      	movs	r1, #1
 8000d9c:	438a      	bics	r2, r1
 8000d9e:	621a      	str	r2, [r3, #32]
 8000da0:	6a1a      	ldr	r2, [r3, #32]
 8000da2:	3103      	adds	r1, #3
 8000da4:	438a      	bics	r2, r1
 8000da6:	621a      	str	r2, [r3, #32]
 8000da8:	e01a      	b.n	8000de0 <HAL_RCC_OscConfig+0x25c>
    FlagStatus       pwrclkchanged = RESET;
 8000daa:	2500      	movs	r5, #0
 8000dac:	e7ea      	b.n	8000d84 <HAL_RCC_OscConfig+0x200>
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8000dae:	4a2b      	ldr	r2, [pc, #172]	; (8000e5c <HAL_RCC_OscConfig+0x2d8>)
 8000db0:	6811      	ldr	r1, [r2, #0]
 8000db2:	2380      	movs	r3, #128	; 0x80
 8000db4:	005b      	lsls	r3, r3, #1
 8000db6:	430b      	orrs	r3, r1
 8000db8:	6013      	str	r3, [r2, #0]
      tickstart = HAL_GetTick();
 8000dba:	f7ff fda9 	bl	8000910 <HAL_GetTick>
 8000dbe:	0006      	movs	r6, r0
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8000dc0:	4b26      	ldr	r3, [pc, #152]	; (8000e5c <HAL_RCC_OscConfig+0x2d8>)
 8000dc2:	681b      	ldr	r3, [r3, #0]
 8000dc4:	05db      	lsls	r3, r3, #23
 8000dc6:	d4e1      	bmi.n	8000d8c <HAL_RCC_OscConfig+0x208>
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8000dc8:	f7ff fda2 	bl	8000910 <HAL_GetTick>
 8000dcc:	1b80      	subs	r0, r0, r6
 8000dce:	2864      	cmp	r0, #100	; 0x64
 8000dd0:	d9f6      	bls.n	8000dc0 <HAL_RCC_OscConfig+0x23c>
          return HAL_TIMEOUT;
 8000dd2:	2003      	movs	r0, #3
 8000dd4:	e10b      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8000dd6:	4a1e      	ldr	r2, [pc, #120]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000dd8:	6a13      	ldr	r3, [r2, #32]
 8000dda:	2101      	movs	r1, #1
 8000ddc:	430b      	orrs	r3, r1
 8000dde:	6213      	str	r3, [r2, #32]
    /* Check the LSE State */
    if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
 8000de0:	68a3      	ldr	r3, [r4, #8]
 8000de2:	2b00      	cmp	r3, #0
 8000de4:	d024      	beq.n	8000e30 <HAL_RCC_OscConfig+0x2ac>
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8000de6:	f7ff fd93 	bl	8000910 <HAL_GetTick>
 8000dea:	0006      	movs	r6, r0
      
      /* Wait till LSE is ready */  
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8000dec:	4b18      	ldr	r3, [pc, #96]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000dee:	6a1b      	ldr	r3, [r3, #32]
 8000df0:	079b      	lsls	r3, r3, #30
 8000df2:	d437      	bmi.n	8000e64 <HAL_RCC_OscConfig+0x2e0>
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8000df4:	f7ff fd8c 	bl	8000910 <HAL_GetTick>
 8000df8:	1b80      	subs	r0, r0, r6
 8000dfa:	4b19      	ldr	r3, [pc, #100]	; (8000e60 <HAL_RCC_OscConfig+0x2dc>)
 8000dfc:	4298      	cmp	r0, r3
 8000dfe:	d9f5      	bls.n	8000dec <HAL_RCC_OscConfig+0x268>
        {
          return HAL_TIMEOUT;
 8000e00:	2003      	movs	r0, #3
 8000e02:	e0f4      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8000e04:	2b05      	cmp	r3, #5
 8000e06:	d009      	beq.n	8000e1c <HAL_RCC_OscConfig+0x298>
 8000e08:	4b11      	ldr	r3, [pc, #68]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000e0a:	6a1a      	ldr	r2, [r3, #32]
 8000e0c:	2101      	movs	r1, #1
 8000e0e:	438a      	bics	r2, r1
 8000e10:	621a      	str	r2, [r3, #32]
 8000e12:	6a1a      	ldr	r2, [r3, #32]
 8000e14:	3103      	adds	r1, #3
 8000e16:	438a      	bics	r2, r1
 8000e18:	621a      	str	r2, [r3, #32]
 8000e1a:	e7e1      	b.n	8000de0 <HAL_RCC_OscConfig+0x25c>
 8000e1c:	4b0c      	ldr	r3, [pc, #48]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000e1e:	6a1a      	ldr	r2, [r3, #32]
 8000e20:	2104      	movs	r1, #4
 8000e22:	430a      	orrs	r2, r1
 8000e24:	621a      	str	r2, [r3, #32]
 8000e26:	6a1a      	ldr	r2, [r3, #32]
 8000e28:	3903      	subs	r1, #3
 8000e2a:	430a      	orrs	r2, r1
 8000e2c:	621a      	str	r2, [r3, #32]
 8000e2e:	e7d7      	b.n	8000de0 <HAL_RCC_OscConfig+0x25c>
      }
    }
    else
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8000e30:	f7ff fd6e 	bl	8000910 <HAL_GetTick>
 8000e34:	0006      	movs	r6, r0
      
      /* Wait till LSE is disabled */  
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8000e36:	4b06      	ldr	r3, [pc, #24]	; (8000e50 <HAL_RCC_OscConfig+0x2cc>)
 8000e38:	6a1b      	ldr	r3, [r3, #32]
 8000e3a:	079b      	lsls	r3, r3, #30
 8000e3c:	d512      	bpl.n	8000e64 <HAL_RCC_OscConfig+0x2e0>
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8000e3e:	f7ff fd67 	bl	8000910 <HAL_GetTick>
 8000e42:	1b80      	subs	r0, r0, r6
 8000e44:	4b06      	ldr	r3, [pc, #24]	; (8000e60 <HAL_RCC_OscConfig+0x2dc>)
 8000e46:	4298      	cmp	r0, r3
 8000e48:	d9f5      	bls.n	8000e36 <HAL_RCC_OscConfig+0x2b2>
        {
          return HAL_TIMEOUT;
 8000e4a:	2003      	movs	r0, #3
 8000e4c:	e0cf      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
 8000e4e:	46c0      	nop			; (mov r8, r8)
 8000e50:	40021000 	.word	0x40021000
 8000e54:	fffeffff 	.word	0xfffeffff
 8000e58:	fffbffff 	.word	0xfffbffff
 8000e5c:	40007000 	.word	0x40007000
 8000e60:	00001388 	.word	0x00001388
        }
      }
    }

    /* Require to disable power clock if necessary */
    if(pwrclkchanged == SET)
 8000e64:	2d01      	cmp	r5, #1
 8000e66:	d033      	beq.n	8000ed0 <HAL_RCC_OscConfig+0x34c>
      __HAL_RCC_PWR_CLK_DISABLE();
    }
  }

  /*----------------------------- HSI14 Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
 8000e68:	6823      	ldr	r3, [r4, #0]
 8000e6a:	06db      	lsls	r3, r3, #27
 8000e6c:	d510      	bpl.n	8000e90 <HAL_RCC_OscConfig+0x30c>
    /* Check the parameters */
    assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));

    /* Check the HSI14 State */
    if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
 8000e6e:	6963      	ldr	r3, [r4, #20]
 8000e70:	2b01      	cmp	r3, #1
 8000e72:	d033      	beq.n	8000edc <HAL_RCC_OscConfig+0x358>
      } 

      /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
      __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
    }
    else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
 8000e74:	3305      	adds	r3, #5
 8000e76:	d151      	bne.n	8000f1c <HAL_RCC_OscConfig+0x398>
    {
      /* Enable ADC control of the Internal High Speed oscillator HSI14 */
      __HAL_RCC_HSI14ADC_ENABLE();
 8000e78:	4a65      	ldr	r2, [pc, #404]	; (8001010 <HAL_RCC_OscConfig+0x48c>)
 8000e7a:	6b53      	ldr	r3, [r2, #52]	; 0x34
 8000e7c:	2104      	movs	r1, #4
 8000e7e:	438b      	bics	r3, r1
 8000e80:	6353      	str	r3, [r2, #52]	; 0x34

      /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
      __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
 8000e82:	6b53      	ldr	r3, [r2, #52]	; 0x34
 8000e84:	31f4      	adds	r1, #244	; 0xf4
 8000e86:	438b      	bics	r3, r1
 8000e88:	69a1      	ldr	r1, [r4, #24]
 8000e8a:	00c9      	lsls	r1, r1, #3
 8000e8c:	430b      	orrs	r3, r1
 8000e8e:	6353      	str	r3, [r2, #52]	; 0x34
#endif /* RCC_HSI48_SUPPORT */
       
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 8000e90:	6a23      	ldr	r3, [r4, #32]
 8000e92:	2b00      	cmp	r3, #0
 8000e94:	d100      	bne.n	8000e98 <HAL_RCC_OscConfig+0x314>
 8000e96:	e0b0      	b.n	8000ffa <HAL_RCC_OscConfig+0x476>
  {
    /* Check if the PLL is used as system clock or not */
    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8000e98:	4a5d      	ldr	r2, [pc, #372]	; (8001010 <HAL_RCC_OscConfig+0x48c>)
 8000e9a:	6851      	ldr	r1, [r2, #4]
 8000e9c:	220c      	movs	r2, #12
 8000e9e:	400a      	ands	r2, r1
 8000ea0:	2a08      	cmp	r2, #8
 8000ea2:	d100      	bne.n	8000ea6 <HAL_RCC_OscConfig+0x322>
 8000ea4:	e08a      	b.n	8000fbc <HAL_RCC_OscConfig+0x438>
    { 
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8000ea6:	2b02      	cmp	r3, #2
 8000ea8:	d04f      	beq.n	8000f4a <HAL_RCC_OscConfig+0x3c6>
        }
      }
      else
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8000eaa:	4a59      	ldr	r2, [pc, #356]	; (8001010 <HAL_RCC_OscConfig+0x48c>)
 8000eac:	6813      	ldr	r3, [r2, #0]
 8000eae:	4959      	ldr	r1, [pc, #356]	; (8001014 <HAL_RCC_OscConfig+0x490>)
 8000eb0:	400b      	ands	r3, r1
 8000eb2:	6013      	str	r3, [r2, #0]
 
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000eb4:	f7ff fd2c 	bl	8000910 <HAL_GetTick>
 8000eb8:	0004      	movs	r4, r0
        
        /* Wait till PLL is disabled */  
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8000eba:	4b55      	ldr	r3, [pc, #340]	; (8001010 <HAL_RCC_OscConfig+0x48c>)
 8000ebc:	681b      	ldr	r3, [r3, #0]
 8000ebe:	019b      	lsls	r3, r3, #6
 8000ec0:	d57a      	bpl.n	8000fb8 <HAL_RCC_OscConfig+0x434>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8000ec2:	f7ff fd25 	bl	8000910 <HAL_GetTick>
 8000ec6:	1b00      	subs	r0, r0, r4
 8000ec8:	2802      	cmp	r0, #2
 8000eca:	d9f6      	bls.n	8000eba <HAL_RCC_OscConfig+0x336>
          {
            return HAL_TIMEOUT;
 8000ecc:	2003      	movs	r0, #3
 8000ece:	e08e      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
      __HAL_RCC_PWR_CLK_DISABLE();
 8000ed0:	4a4f      	ldr	r2, [pc, #316]	; (8001010 <HAL_RCC_OscConfig+0x48c>)
 8000ed2:	69d3      	ldr	r3, [r2, #28]
 8000ed4:	4950      	ldr	r1, [pc, #320]	; (8001018 <HAL_RCC_OscConfig+0x494>)
 8000ed6:	400b      	ands	r3, r1
 8000ed8:	61d3      	str	r3, [r2, #28]
 8000eda:	e7c5      	b.n	8000e68 <HAL_RCC_OscConfig+0x2e4>
      __HAL_RCC_HSI14ADC_DISABLE();
 8000edc:	4b4c      	ldr	r3, [pc, #304]	; (8001010 <HAL_RCC_OscConfig+0x48c>)
 8000ede:	6b5a      	ldr	r2, [r3, #52]	; 0x34
 8000ee0:	2104      	movs	r1, #4
 8000ee2:	430a      	orrs	r2, r1
 8000ee4:	635a      	str	r2, [r3, #52]	; 0x34
      __HAL_RCC_HSI14_ENABLE();
 8000ee6:	6b5a      	ldr	r2, [r3, #52]	; 0x34
 8000ee8:	3903      	subs	r1, #3
 8000eea:	430a      	orrs	r2, r1
 8000eec:	635a      	str	r2, [r3, #52]	; 0x34
      tickstart = HAL_GetTick();
 8000eee:	f7ff fd0f 	bl	8000910 <HAL_GetTick>
 8000ef2:	0005      	movs	r5, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
 8000ef4:	4b46      	ldr	r3, [pc, #280]	; (8001010 <HAL_RCC_OscConfig+0x48c>)
 8000ef6:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8000ef8:	079b      	lsls	r3, r3, #30
 8000efa:	d406      	bmi.n	8000f0a <HAL_RCC_OscConfig+0x386>
        if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
 8000efc:	f7ff fd08 	bl	8000910 <HAL_GetTick>
 8000f00:	1b40      	subs	r0, r0, r5
 8000f02:	2802      	cmp	r0, #2
 8000f04:	d9f6      	bls.n	8000ef4 <HAL_RCC_OscConfig+0x370>
          return HAL_TIMEOUT;
 8000f06:	2003      	movs	r0, #3
 8000f08:	e071      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
      __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
 8000f0a:	4941      	ldr	r1, [pc, #260]	; (8001010 <HAL_RCC_OscConfig+0x48c>)
 8000f0c:	6b4b      	ldr	r3, [r1, #52]	; 0x34
 8000f0e:	22f8      	movs	r2, #248	; 0xf8
 8000f10:	4393      	bics	r3, r2
 8000f12:	69a2      	ldr	r2, [r4, #24]
 8000f14:	00d2      	lsls	r2, r2, #3
 8000f16:	4313      	orrs	r3, r2
 8000f18:	634b      	str	r3, [r1, #52]	; 0x34
 8000f1a:	e7b9      	b.n	8000e90 <HAL_RCC_OscConfig+0x30c>
      __HAL_RCC_HSI14ADC_DISABLE();
 8000f1c:	4b3c      	ldr	r3, [pc, #240]	; (8001010 <HAL_RCC_OscConfig+0x48c>)
 8000f1e:	6b5a      	ldr	r2, [r3, #52]	; 0x34
 8000f20:	2104      	movs	r1, #4
 8000f22:	430a      	orrs	r2, r1
 8000f24:	635a      	str	r2, [r3, #52]	; 0x34
      __HAL_RCC_HSI14_DISABLE();
 8000f26:	6b5a      	ldr	r2, [r3, #52]	; 0x34
 8000f28:	3903      	subs	r1, #3
 8000f2a:	438a      	bics	r2, r1
 8000f2c:	635a      	str	r2, [r3, #52]	; 0x34
      tickstart = HAL_GetTick();
 8000f2e:	f7ff fcef 	bl	8000910 <HAL_GetTick>
 8000f32:	0005      	movs	r5, r0
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
 8000f34:	4b36      	ldr	r3, [pc, #216]	; (8001010 <HAL_RCC_OscConfig+0x48c>)
 8000f36:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8000f38:	079b      	lsls	r3, r3, #30
 8000f3a:	d5a9      	bpl.n	8000e90 <HAL_RCC_OscConfig+0x30c>
        if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
 8000f3c:	f7ff fce8 	bl	8000910 <HAL_GetTick>
 8000f40:	1b40      	subs	r0, r0, r5
 8000f42:	2802      	cmp	r0, #2
 8000f44:	d9f6      	bls.n	8000f34 <HAL_RCC_OscConfig+0x3b0>
          return HAL_TIMEOUT;
 8000f46:	2003      	movs	r0, #3
 8000f48:	e051      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
        __HAL_RCC_PLL_DISABLE();
 8000f4a:	4a31      	ldr	r2, [pc, #196]	; (8001010 <HAL_RCC_OscConfig+0x48c>)
 8000f4c:	6813      	ldr	r3, [r2, #0]
 8000f4e:	4931      	ldr	r1, [pc, #196]	; (8001014 <HAL_RCC_OscConfig+0x490>)
 8000f50:	400b      	ands	r3, r1
 8000f52:	6013      	str	r3, [r2, #0]
        tickstart = HAL_GetTick();
 8000f54:	f7ff fcdc 	bl	8000910 <HAL_GetTick>
 8000f58:	0005      	movs	r5, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8000f5a:	4b2d      	ldr	r3, [pc, #180]	; (8001010 <HAL_RCC_OscConfig+0x48c>)
 8000f5c:	681b      	ldr	r3, [r3, #0]
 8000f5e:	019b      	lsls	r3, r3, #6
 8000f60:	d506      	bpl.n	8000f70 <HAL_RCC_OscConfig+0x3ec>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8000f62:	f7ff fcd5 	bl	8000910 <HAL_GetTick>
 8000f66:	1b40      	subs	r0, r0, r5
 8000f68:	2802      	cmp	r0, #2
 8000f6a:	d9f6      	bls.n	8000f5a <HAL_RCC_OscConfig+0x3d6>
            return HAL_TIMEOUT;
 8000f6c:	2003      	movs	r0, #3
 8000f6e:	e03e      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 8000f70:	4b27      	ldr	r3, [pc, #156]	; (8001010 <HAL_RCC_OscConfig+0x48c>)
 8000f72:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8000f74:	210f      	movs	r1, #15
 8000f76:	438a      	bics	r2, r1
 8000f78:	6ae1      	ldr	r1, [r4, #44]	; 0x2c
 8000f7a:	430a      	orrs	r2, r1
 8000f7c:	62da      	str	r2, [r3, #44]	; 0x2c
 8000f7e:	685a      	ldr	r2, [r3, #4]
 8000f80:	4926      	ldr	r1, [pc, #152]	; (800101c <HAL_RCC_OscConfig+0x498>)
 8000f82:	400a      	ands	r2, r1
 8000f84:	6aa1      	ldr	r1, [r4, #40]	; 0x28
 8000f86:	6a60      	ldr	r0, [r4, #36]	; 0x24
 8000f88:	4301      	orrs	r1, r0
 8000f8a:	430a      	orrs	r2, r1
 8000f8c:	605a      	str	r2, [r3, #4]
        __HAL_RCC_PLL_ENABLE();
 8000f8e:	6819      	ldr	r1, [r3, #0]
 8000f90:	2280      	movs	r2, #128	; 0x80
 8000f92:	0452      	lsls	r2, r2, #17
 8000f94:	430a      	orrs	r2, r1
 8000f96:	601a      	str	r2, [r3, #0]
        tickstart = HAL_GetTick();
 8000f98:	f7ff fcba 	bl	8000910 <HAL_GetTick>
 8000f9c:	0004      	movs	r4, r0
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
 8000f9e:	4b1c      	ldr	r3, [pc, #112]	; (8001010 <HAL_RCC_OscConfig+0x48c>)
 8000fa0:	681b      	ldr	r3, [r3, #0]
 8000fa2:	019b      	lsls	r3, r3, #6
 8000fa4:	d406      	bmi.n	8000fb4 <HAL_RCC_OscConfig+0x430>
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8000fa6:	f7ff fcb3 	bl	8000910 <HAL_GetTick>
 8000faa:	1b00      	subs	r0, r0, r4
 8000fac:	2802      	cmp	r0, #2
 8000fae:	d9f6      	bls.n	8000f9e <HAL_RCC_OscConfig+0x41a>
            return HAL_TIMEOUT;
 8000fb0:	2003      	movs	r0, #3
 8000fb2:	e01c      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
        }
      }
    }
  }

  return HAL_OK;
 8000fb4:	2000      	movs	r0, #0
 8000fb6:	e01a      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
 8000fb8:	2000      	movs	r0, #0
 8000fba:	e018      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
 8000fbc:	2b01      	cmp	r3, #1
 8000fbe:	d01e      	beq.n	8000ffe <HAL_RCC_OscConfig+0x47a>
        pll_config  = RCC->CFGR;
 8000fc0:	4b13      	ldr	r3, [pc, #76]	; (8001010 <HAL_RCC_OscConfig+0x48c>)
 8000fc2:	685a      	ldr	r2, [r3, #4]
        pll_config2 = RCC->CFGR2;
 8000fc4:	6ad9      	ldr	r1, [r3, #44]	; 0x2c
        if((READ_BIT(pll_config,  RCC_CFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||
 8000fc6:	2380      	movs	r3, #128	; 0x80
 8000fc8:	025b      	lsls	r3, r3, #9
 8000fca:	4013      	ands	r3, r2
 8000fcc:	6a60      	ldr	r0, [r4, #36]	; 0x24
 8000fce:	4283      	cmp	r3, r0
 8000fd0:	d117      	bne.n	8001002 <HAL_RCC_OscConfig+0x47e>
           (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)    ||
 8000fd2:	230f      	movs	r3, #15
 8000fd4:	400b      	ands	r3, r1
        if((READ_BIT(pll_config,  RCC_CFGR_PLLSRC)  != RCC_OscInitStruct->PLL.PLLSource) ||
 8000fd6:	6ae1      	ldr	r1, [r4, #44]	; 0x2c
 8000fd8:	428b      	cmp	r3, r1
 8000fda:	d114      	bne.n	8001006 <HAL_RCC_OscConfig+0x482>
           (READ_BIT(pll_config,  RCC_CFGR_PLLMUL)  != RCC_OscInitStruct->PLL.PLLMUL))
 8000fdc:	23f0      	movs	r3, #240	; 0xf0
 8000fde:	039b      	lsls	r3, r3, #14
 8000fe0:	401a      	ands	r2, r3
 8000fe2:	6aa3      	ldr	r3, [r4, #40]	; 0x28
           (READ_BIT(pll_config2, RCC_CFGR2_PREDIV) != RCC_OscInitStruct->PLL.PREDIV)    ||
 8000fe4:	429a      	cmp	r2, r3
 8000fe6:	d110      	bne.n	800100a <HAL_RCC_OscConfig+0x486>
  return HAL_OK;
 8000fe8:	2000      	movs	r0, #0
 8000fea:	e000      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
    return HAL_ERROR;
 8000fec:	2001      	movs	r0, #1
}
 8000fee:	b002      	add	sp, #8
 8000ff0:	bd70      	pop	{r4, r5, r6, pc}
        return HAL_ERROR;
 8000ff2:	2001      	movs	r0, #1
 8000ff4:	e7fb      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
        return HAL_ERROR;
 8000ff6:	2001      	movs	r0, #1
 8000ff8:	e7f9      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
  return HAL_OK;
 8000ffa:	2000      	movs	r0, #0
 8000ffc:	e7f7      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
        return HAL_ERROR;
 8000ffe:	2001      	movs	r0, #1
 8001000:	e7f5      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
          return HAL_ERROR;
 8001002:	2001      	movs	r0, #1
 8001004:	e7f3      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
 8001006:	2001      	movs	r0, #1
 8001008:	e7f1      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
 800100a:	2001      	movs	r0, #1
 800100c:	e7ef      	b.n	8000fee <HAL_RCC_OscConfig+0x46a>
 800100e:	46c0      	nop			; (mov r8, r8)
 8001010:	40021000 	.word	0x40021000
 8001014:	feffffff 	.word	0xfeffffff
 8001018:	efffffff 	.word	0xefffffff
 800101c:	ffc2ffff 	.word	0xffc2ffff

08001020 <HAL_RCC_GetSysClockFreq>:
  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
  *         
  * @retval SYSCLK frequency
  */
uint32_t HAL_RCC_GetSysClockFreq(void)
{
 8001020:	b510      	push	{r4, lr}
 8001022:	b088      	sub	sp, #32
  const uint8_t aPLLMULFactorTable[16] = { 2U,  3U,  4U,  5U,  6U,  7U,  8U,  9U,
 8001024:	aa04      	add	r2, sp, #16
 8001026:	4b16      	ldr	r3, [pc, #88]	; (8001080 <HAL_RCC_GetSysClockFreq+0x60>)
 8001028:	cb13      	ldmia	r3!, {r0, r1, r4}
 800102a:	c213      	stmia	r2!, {r0, r1, r4}
 800102c:	681b      	ldr	r3, [r3, #0]
 800102e:	6013      	str	r3, [r2, #0]
                                         10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
  const uint8_t aPredivFactorTable[16] = { 1U, 2U,  3U,  4U,  5U,  6U,  7U,  8U,
 8001030:	466a      	mov	r2, sp
 8001032:	4b14      	ldr	r3, [pc, #80]	; (8001084 <HAL_RCC_GetSysClockFreq+0x64>)
 8001034:	cb13      	ldmia	r3!, {r0, r1, r4}
 8001036:	c213      	stmia	r2!, {r0, r1, r4}
 8001038:	681b      	ldr	r3, [r3, #0]
 800103a:	6013      	str	r3, [r2, #0]
                                           9U,10U, 11U, 12U, 13U, 14U, 15U, 16U};

  uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
  uint32_t sysclockfreq = 0U;
  
  tmpreg = RCC->CFGR;
 800103c:	4b12      	ldr	r3, [pc, #72]	; (8001088 <HAL_RCC_GetSysClockFreq+0x68>)
 800103e:	685a      	ldr	r2, [r3, #4]
  
  /* Get SYSCLK source -------------------------------------------------------*/
  switch (tmpreg & RCC_CFGR_SWS)
 8001040:	230c      	movs	r3, #12
 8001042:	4013      	ands	r3, r2
 8001044:	2b08      	cmp	r3, #8
 8001046:	d002      	beq.n	800104e <HAL_RCC_GetSysClockFreq+0x2e>
  {
    case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
    {
      sysclockfreq = HSE_VALUE;
 8001048:	4810      	ldr	r0, [pc, #64]	; (800108c <HAL_RCC_GetSysClockFreq+0x6c>)
      sysclockfreq = HSI_VALUE;
      break;
    }
  }
  return sysclockfreq;
}
 800104a:	b008      	add	sp, #32
 800104c:	bd10      	pop	{r4, pc}
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
 800104e:	0c91      	lsrs	r1, r2, #18
 8001050:	3307      	adds	r3, #7
 8001052:	4019      	ands	r1, r3
 8001054:	a804      	add	r0, sp, #16
 8001056:	5c44      	ldrb	r4, [r0, r1]
      prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
 8001058:	490b      	ldr	r1, [pc, #44]	; (8001088 <HAL_RCC_GetSysClockFreq+0x68>)
 800105a:	6ac9      	ldr	r1, [r1, #44]	; 0x2c
 800105c:	400b      	ands	r3, r1
 800105e:	4669      	mov	r1, sp
 8001060:	5cc9      	ldrb	r1, [r1, r3]
      if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
 8001062:	03d3      	lsls	r3, r2, #15
 8001064:	d504      	bpl.n	8001070 <HAL_RCC_GetSysClockFreq+0x50>
        pllclk = (uint32_t)((uint64_t) HSE_VALUE / (uint64_t) (prediv)) * ((uint64_t) pllmul);
 8001066:	4809      	ldr	r0, [pc, #36]	; (800108c <HAL_RCC_GetSysClockFreq+0x6c>)
 8001068:	f7ff f84e 	bl	8000108 <__udivsi3>
 800106c:	4360      	muls	r0, r4
 800106e:	e7ec      	b.n	800104a <HAL_RCC_GetSysClockFreq+0x2a>
        pllclk = (uint32_t)((uint64_t) (HSI_VALUE >> 1U) * ((uint64_t) pllmul));
 8001070:	0163      	lsls	r3, r4, #5
 8001072:	1b1b      	subs	r3, r3, r4
 8001074:	0198      	lsls	r0, r3, #6
 8001076:	1ac0      	subs	r0, r0, r3
 8001078:	00c0      	lsls	r0, r0, #3
 800107a:	1900      	adds	r0, r0, r4
 800107c:	0200      	lsls	r0, r0, #8
 800107e:	e7e4      	b.n	800104a <HAL_RCC_GetSysClockFreq+0x2a>
 8001080:	08001a9c 	.word	0x08001a9c
 8001084:	08001ab0 	.word	0x08001ab0
 8001088:	40021000 	.word	0x40021000
 800108c:	007a1200 	.word	0x007a1200

08001090 <HAL_RCC_ClockConfig>:
{
 8001090:	b570      	push	{r4, r5, r6, lr}
 8001092:	0004      	movs	r4, r0
 8001094:	000d      	movs	r5, r1
  if(RCC_ClkInitStruct == NULL)
 8001096:	2800      	cmp	r0, #0
 8001098:	d100      	bne.n	800109c <HAL_RCC_ClockConfig+0xc>
 800109a:	e07e      	b.n	800119a <HAL_RCC_ClockConfig+0x10a>
  if(FLatency > __HAL_FLASH_GET_LATENCY())
 800109c:	4b43      	ldr	r3, [pc, #268]	; (80011ac <HAL_RCC_ClockConfig+0x11c>)
 800109e:	681a      	ldr	r2, [r3, #0]
 80010a0:	2301      	movs	r3, #1
 80010a2:	4013      	ands	r3, r2
 80010a4:	428b      	cmp	r3, r1
 80010a6:	d20a      	bcs.n	80010be <HAL_RCC_ClockConfig+0x2e>
    __HAL_FLASH_SET_LATENCY(FLatency);
 80010a8:	4940      	ldr	r1, [pc, #256]	; (80011ac <HAL_RCC_ClockConfig+0x11c>)
 80010aa:	680b      	ldr	r3, [r1, #0]
 80010ac:	2201      	movs	r2, #1
 80010ae:	4393      	bics	r3, r2
 80010b0:	432b      	orrs	r3, r5
 80010b2:	600b      	str	r3, [r1, #0]
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 80010b4:	680b      	ldr	r3, [r1, #0]
 80010b6:	401a      	ands	r2, r3
 80010b8:	42aa      	cmp	r2, r5
 80010ba:	d000      	beq.n	80010be <HAL_RCC_ClockConfig+0x2e>
 80010bc:	e06f      	b.n	800119e <HAL_RCC_ClockConfig+0x10e>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 80010be:	6823      	ldr	r3, [r4, #0]
 80010c0:	079a      	lsls	r2, r3, #30
 80010c2:	d50e      	bpl.n	80010e2 <HAL_RCC_ClockConfig+0x52>
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 80010c4:	075b      	lsls	r3, r3, #29
 80010c6:	d505      	bpl.n	80010d4 <HAL_RCC_ClockConfig+0x44>
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
 80010c8:	4a39      	ldr	r2, [pc, #228]	; (80011b0 <HAL_RCC_ClockConfig+0x120>)
 80010ca:	6851      	ldr	r1, [r2, #4]
 80010cc:	23e0      	movs	r3, #224	; 0xe0
 80010ce:	00db      	lsls	r3, r3, #3
 80010d0:	430b      	orrs	r3, r1
 80010d2:	6053      	str	r3, [r2, #4]
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 80010d4:	4a36      	ldr	r2, [pc, #216]	; (80011b0 <HAL_RCC_ClockConfig+0x120>)
 80010d6:	6853      	ldr	r3, [r2, #4]
 80010d8:	21f0      	movs	r1, #240	; 0xf0
 80010da:	438b      	bics	r3, r1
 80010dc:	68a1      	ldr	r1, [r4, #8]
 80010de:	430b      	orrs	r3, r1
 80010e0:	6053      	str	r3, [r2, #4]
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 80010e2:	6823      	ldr	r3, [r4, #0]
 80010e4:	07db      	lsls	r3, r3, #31
 80010e6:	d52d      	bpl.n	8001144 <HAL_RCC_ClockConfig+0xb4>
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 80010e8:	6863      	ldr	r3, [r4, #4]
 80010ea:	2b01      	cmp	r3, #1
 80010ec:	d01e      	beq.n	800112c <HAL_RCC_ClockConfig+0x9c>
    else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 80010ee:	2b02      	cmp	r3, #2
 80010f0:	d022      	beq.n	8001138 <HAL_RCC_ClockConfig+0xa8>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 80010f2:	4a2f      	ldr	r2, [pc, #188]	; (80011b0 <HAL_RCC_ClockConfig+0x120>)
 80010f4:	6812      	ldr	r2, [r2, #0]
 80010f6:	0792      	lsls	r2, r2, #30
 80010f8:	d553      	bpl.n	80011a2 <HAL_RCC_ClockConfig+0x112>
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 80010fa:	492d      	ldr	r1, [pc, #180]	; (80011b0 <HAL_RCC_ClockConfig+0x120>)
 80010fc:	684a      	ldr	r2, [r1, #4]
 80010fe:	2003      	movs	r0, #3
 8001100:	4382      	bics	r2, r0
 8001102:	4313      	orrs	r3, r2
 8001104:	604b      	str	r3, [r1, #4]
    tickstart = HAL_GetTick();
 8001106:	f7ff fc03 	bl	8000910 <HAL_GetTick>
 800110a:	0006      	movs	r6, r0
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 800110c:	4b28      	ldr	r3, [pc, #160]	; (80011b0 <HAL_RCC_ClockConfig+0x120>)
 800110e:	685b      	ldr	r3, [r3, #4]
 8001110:	220c      	movs	r2, #12
 8001112:	401a      	ands	r2, r3
 8001114:	6863      	ldr	r3, [r4, #4]
 8001116:	009b      	lsls	r3, r3, #2
 8001118:	429a      	cmp	r2, r3
 800111a:	d013      	beq.n	8001144 <HAL_RCC_ClockConfig+0xb4>
      if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
 800111c:	f7ff fbf8 	bl	8000910 <HAL_GetTick>
 8001120:	1b80      	subs	r0, r0, r6
 8001122:	4b24      	ldr	r3, [pc, #144]	; (80011b4 <HAL_RCC_ClockConfig+0x124>)
 8001124:	4298      	cmp	r0, r3
 8001126:	d9f1      	bls.n	800110c <HAL_RCC_ClockConfig+0x7c>
        return HAL_TIMEOUT;
 8001128:	2003      	movs	r0, #3
 800112a:	e035      	b.n	8001198 <HAL_RCC_ClockConfig+0x108>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 800112c:	4a20      	ldr	r2, [pc, #128]	; (80011b0 <HAL_RCC_ClockConfig+0x120>)
 800112e:	6812      	ldr	r2, [r2, #0]
 8001130:	0392      	lsls	r2, r2, #14
 8001132:	d4e2      	bmi.n	80010fa <HAL_RCC_ClockConfig+0x6a>
        return HAL_ERROR;
 8001134:	2001      	movs	r0, #1
 8001136:	e02f      	b.n	8001198 <HAL_RCC_ClockConfig+0x108>
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 8001138:	4a1d      	ldr	r2, [pc, #116]	; (80011b0 <HAL_RCC_ClockConfig+0x120>)
 800113a:	6812      	ldr	r2, [r2, #0]
 800113c:	0192      	lsls	r2, r2, #6
 800113e:	d4dc      	bmi.n	80010fa <HAL_RCC_ClockConfig+0x6a>
        return HAL_ERROR;
 8001140:	2001      	movs	r0, #1
 8001142:	e029      	b.n	8001198 <HAL_RCC_ClockConfig+0x108>
  if(FLatency < __HAL_FLASH_GET_LATENCY())
 8001144:	4b19      	ldr	r3, [pc, #100]	; (80011ac <HAL_RCC_ClockConfig+0x11c>)
 8001146:	681a      	ldr	r2, [r3, #0]
 8001148:	2301      	movs	r3, #1
 800114a:	4013      	ands	r3, r2
 800114c:	42ab      	cmp	r3, r5
 800114e:	d909      	bls.n	8001164 <HAL_RCC_ClockConfig+0xd4>
    __HAL_FLASH_SET_LATENCY(FLatency);
 8001150:	4916      	ldr	r1, [pc, #88]	; (80011ac <HAL_RCC_ClockConfig+0x11c>)
 8001152:	680b      	ldr	r3, [r1, #0]
 8001154:	2201      	movs	r2, #1
 8001156:	4393      	bics	r3, r2
 8001158:	432b      	orrs	r3, r5
 800115a:	600b      	str	r3, [r1, #0]
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 800115c:	680b      	ldr	r3, [r1, #0]
 800115e:	401a      	ands	r2, r3
 8001160:	42aa      	cmp	r2, r5
 8001162:	d120      	bne.n	80011a6 <HAL_RCC_ClockConfig+0x116>
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8001164:	6823      	ldr	r3, [r4, #0]
 8001166:	075b      	lsls	r3, r3, #29
 8001168:	d506      	bpl.n	8001178 <HAL_RCC_ClockConfig+0xe8>
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
 800116a:	4a11      	ldr	r2, [pc, #68]	; (80011b0 <HAL_RCC_ClockConfig+0x120>)
 800116c:	6853      	ldr	r3, [r2, #4]
 800116e:	4912      	ldr	r1, [pc, #72]	; (80011b8 <HAL_RCC_ClockConfig+0x128>)
 8001170:	400b      	ands	r3, r1
 8001172:	68e1      	ldr	r1, [r4, #12]
 8001174:	430b      	orrs	r3, r1
 8001176:	6053      	str	r3, [r2, #4]
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
 8001178:	f7ff ff52 	bl	8001020 <HAL_RCC_GetSysClockFreq>
 800117c:	4b0c      	ldr	r3, [pc, #48]	; (80011b0 <HAL_RCC_ClockConfig+0x120>)
 800117e:	685a      	ldr	r2, [r3, #4]
 8001180:	0912      	lsrs	r2, r2, #4
 8001182:	230f      	movs	r3, #15
 8001184:	4013      	ands	r3, r2
 8001186:	4a0d      	ldr	r2, [pc, #52]	; (80011bc <HAL_RCC_ClockConfig+0x12c>)
 8001188:	5cd3      	ldrb	r3, [r2, r3]
 800118a:	40d8      	lsrs	r0, r3
 800118c:	4b0c      	ldr	r3, [pc, #48]	; (80011c0 <HAL_RCC_ClockConfig+0x130>)
 800118e:	6018      	str	r0, [r3, #0]
  HAL_InitTick (TICK_INT_PRIORITY);
 8001190:	2003      	movs	r0, #3
 8001192:	f7ff fb79 	bl	8000888 <HAL_InitTick>
  return HAL_OK;
 8001196:	2000      	movs	r0, #0
}
 8001198:	bd70      	pop	{r4, r5, r6, pc}
    return HAL_ERROR;
 800119a:	2001      	movs	r0, #1
 800119c:	e7fc      	b.n	8001198 <HAL_RCC_ClockConfig+0x108>
      return HAL_ERROR;
 800119e:	2001      	movs	r0, #1
 80011a0:	e7fa      	b.n	8001198 <HAL_RCC_ClockConfig+0x108>
        return HAL_ERROR;
 80011a2:	2001      	movs	r0, #1
 80011a4:	e7f8      	b.n	8001198 <HAL_RCC_ClockConfig+0x108>
      return HAL_ERROR;
 80011a6:	2001      	movs	r0, #1
 80011a8:	e7f6      	b.n	8001198 <HAL_RCC_ClockConfig+0x108>
 80011aa:	46c0      	nop			; (mov r8, r8)
 80011ac:	40022000 	.word	0x40022000
 80011b0:	40021000 	.word	0x40021000
 80011b4:	00001388 	.word	0x00001388
 80011b8:	fffff8ff 	.word	0xfffff8ff
 80011bc:	08001a8c 	.word	0x08001a8c
 80011c0:	20000004 	.word	0x20000004

080011c4 <HAL_SPI_Init>:
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
  *               the configuration information for SPI module.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
 80011c4:	b570      	push	{r4, r5, r6, lr}
 80011c6:	1e04      	subs	r4, r0, #0
  uint32_t frxth;

  /* Check the SPI handle allocation */
  if (hspi == NULL)
 80011c8:	d100      	bne.n	80011cc <HAL_SPI_Init+0x8>
 80011ca:	e078      	b.n	80012be <HAL_SPI_Init+0xfa>
  assert_param(IS_SPI_NSS(hspi->Init.NSS));
  assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
  if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
 80011cc:	6a43      	ldr	r3, [r0, #36]	; 0x24
 80011ce:	2b00      	cmp	r3, #0
 80011d0:	d107      	bne.n	80011e2 <HAL_SPI_Init+0x1e>
  {
    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));

    if (hspi->Init.Mode == SPI_MODE_MASTER)
 80011d2:	3305      	adds	r3, #5
 80011d4:	33ff      	adds	r3, #255	; 0xff
 80011d6:	6842      	ldr	r2, [r0, #4]
 80011d8:	429a      	cmp	r2, r3
 80011da:	d005      	beq.n	80011e8 <HAL_SPI_Init+0x24>
      assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
    }
    else
    {
      /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
      hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
 80011dc:	2300      	movs	r3, #0
 80011de:	61c3      	str	r3, [r0, #28]
 80011e0:	e002      	b.n	80011e8 <HAL_SPI_Init+0x24>
  else
  {
    assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));

    /* Force polarity and phase to TI protocaol requirements */
    hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
 80011e2:	2300      	movs	r3, #0
 80011e4:	6103      	str	r3, [r0, #16]
    hspi->Init.CLKPhase    = SPI_PHASE_1EDGE;
 80011e6:	6143      	str	r3, [r0, #20]
  {
    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
    assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
  }
#else
  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
 80011e8:	2300      	movs	r3, #0
 80011ea:	62a3      	str	r3, [r4, #40]	; 0x28
#endif /* USE_SPI_CRC */

  if (hspi->State == HAL_SPI_STATE_RESET)
 80011ec:	335d      	adds	r3, #93	; 0x5d
 80011ee:	5ce3      	ldrb	r3, [r4, r3]
 80011f0:	2b00      	cmp	r3, #0
 80011f2:	d05a      	beq.n	80012aa <HAL_SPI_Init+0xe6>
    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
    HAL_SPI_MspInit(hspi);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
  }

  hspi->State = HAL_SPI_STATE_BUSY;
 80011f4:	235d      	movs	r3, #93	; 0x5d
 80011f6:	2202      	movs	r2, #2
 80011f8:	54e2      	strb	r2, [r4, r3]

  /* Disable the selected SPI peripheral */
  __HAL_SPI_DISABLE(hspi);
 80011fa:	6822      	ldr	r2, [r4, #0]
 80011fc:	6813      	ldr	r3, [r2, #0]
 80011fe:	2140      	movs	r1, #64	; 0x40
 8001200:	438b      	bics	r3, r1
 8001202:	6013      	str	r3, [r2, #0]

  /* Align by default the rs fifo threshold on the data size */
  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
 8001204:	68e3      	ldr	r3, [r4, #12]
 8001206:	22e0      	movs	r2, #224	; 0xe0
 8001208:	00d2      	lsls	r2, r2, #3
 800120a:	4293      	cmp	r3, r2
 800120c:	d954      	bls.n	80012b8 <HAL_SPI_Init+0xf4>
  {
    frxth = SPI_RXFIFO_THRESHOLD_HF;
 800120e:	2200      	movs	r2, #0
  {
    frxth = SPI_RXFIFO_THRESHOLD_QF;
  }

  /* CRC calculation is valid only for 16Bit and 8 Bit */
  if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT))
 8001210:	21f0      	movs	r1, #240	; 0xf0
 8001212:	0109      	lsls	r1, r1, #4
 8001214:	428b      	cmp	r3, r1
 8001216:	d005      	beq.n	8001224 <HAL_SPI_Init+0x60>
 8001218:	21e0      	movs	r1, #224	; 0xe0
 800121a:	00c9      	lsls	r1, r1, #3
 800121c:	428b      	cmp	r3, r1
 800121e:	d001      	beq.n	8001224 <HAL_SPI_Init+0x60>
  {
    /* CRC must be disabled */
    hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
 8001220:	2300      	movs	r3, #0
 8001222:	62a3      	str	r3, [r4, #40]	; 0x28
  }

  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
  /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
  Communication speed, First bit and CRC calculation state */
  WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
 8001224:	2382      	movs	r3, #130	; 0x82
 8001226:	005b      	lsls	r3, r3, #1
 8001228:	6861      	ldr	r1, [r4, #4]
 800122a:	400b      	ands	r3, r1
 800122c:	2184      	movs	r1, #132	; 0x84
 800122e:	0209      	lsls	r1, r1, #8
 8001230:	68a0      	ldr	r0, [r4, #8]
 8001232:	4001      	ands	r1, r0
 8001234:	430b      	orrs	r3, r1
 8001236:	2102      	movs	r1, #2
 8001238:	6920      	ldr	r0, [r4, #16]
 800123a:	4001      	ands	r1, r0
 800123c:	430b      	orrs	r3, r1
 800123e:	2101      	movs	r1, #1
 8001240:	6960      	ldr	r0, [r4, #20]
 8001242:	4008      	ands	r0, r1
 8001244:	4303      	orrs	r3, r0
 8001246:	2080      	movs	r0, #128	; 0x80
 8001248:	0080      	lsls	r0, r0, #2
 800124a:	69a5      	ldr	r5, [r4, #24]
 800124c:	4028      	ands	r0, r5
 800124e:	4303      	orrs	r3, r0
 8001250:	2038      	movs	r0, #56	; 0x38
 8001252:	69e5      	ldr	r5, [r4, #28]
 8001254:	4028      	ands	r0, r5
 8001256:	4303      	orrs	r3, r0
 8001258:	2080      	movs	r0, #128	; 0x80
 800125a:	6a25      	ldr	r5, [r4, #32]
 800125c:	4028      	ands	r0, r5
 800125e:	4303      	orrs	r3, r0
 8001260:	2080      	movs	r0, #128	; 0x80
 8001262:	0180      	lsls	r0, r0, #6
 8001264:	6aa5      	ldr	r5, [r4, #40]	; 0x28
 8001266:	4028      	ands	r0, r5
 8001268:	4303      	orrs	r3, r0
 800126a:	6820      	ldr	r0, [r4, #0]
 800126c:	6003      	str	r3, [r0, #0]
    }
  }
#endif /* USE_SPI_CRC */

  /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */
  WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) |
 800126e:	8b60      	ldrh	r0, [r4, #26]
 8001270:	2304      	movs	r3, #4
 8001272:	4003      	ands	r3, r0
 8001274:	2010      	movs	r0, #16
 8001276:	6a65      	ldr	r5, [r4, #36]	; 0x24
 8001278:	4028      	ands	r0, r5
 800127a:	4303      	orrs	r3, r0
 800127c:	2008      	movs	r0, #8
 800127e:	6b65      	ldr	r5, [r4, #52]	; 0x34
 8001280:	4028      	ands	r0, r5
 8001282:	4303      	orrs	r3, r0
 8001284:	20f0      	movs	r0, #240	; 0xf0
 8001286:	0100      	lsls	r0, r0, #4
 8001288:	68e5      	ldr	r5, [r4, #12]
 800128a:	4028      	ands	r0, r5
 800128c:	4303      	orrs	r3, r0
 800128e:	6820      	ldr	r0, [r4, #0]
 8001290:	4313      	orrs	r3, r2
 8001292:	6043      	str	r3, [r0, #4]
  }
#endif /* USE_SPI_CRC */

#if defined(SPI_I2SCFGR_I2SMOD)
  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
 8001294:	6822      	ldr	r2, [r4, #0]
 8001296:	69d3      	ldr	r3, [r2, #28]
 8001298:	480a      	ldr	r0, [pc, #40]	; (80012c4 <HAL_SPI_Init+0x100>)
 800129a:	4003      	ands	r3, r0
 800129c:	61d3      	str	r3, [r2, #28]
#endif /* SPI_I2SCFGR_I2SMOD */

  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
 800129e:	2300      	movs	r3, #0
 80012a0:	6623      	str	r3, [r4, #96]	; 0x60
  hspi->State     = HAL_SPI_STATE_READY;
 80012a2:	335d      	adds	r3, #93	; 0x5d
 80012a4:	54e1      	strb	r1, [r4, r3]

  return HAL_OK;
 80012a6:	2000      	movs	r0, #0
}
 80012a8:	bd70      	pop	{r4, r5, r6, pc}
    hspi->Lock = HAL_UNLOCKED;
 80012aa:	335c      	adds	r3, #92	; 0x5c
 80012ac:	2200      	movs	r2, #0
 80012ae:	54e2      	strb	r2, [r4, r3]
    HAL_SPI_MspInit(hspi);
 80012b0:	0020      	movs	r0, r4
 80012b2:	f7ff f9ad 	bl	8000610 <HAL_SPI_MspInit>
 80012b6:	e79d      	b.n	80011f4 <HAL_SPI_Init+0x30>
    frxth = SPI_RXFIFO_THRESHOLD_QF;
 80012b8:	2280      	movs	r2, #128	; 0x80
 80012ba:	0152      	lsls	r2, r2, #5
 80012bc:	e7a8      	b.n	8001210 <HAL_SPI_Init+0x4c>
    return HAL_ERROR;
 80012be:	2001      	movs	r0, #1
 80012c0:	e7f2      	b.n	80012a8 <HAL_SPI_Init+0xe4>
 80012c2:	46c0      	nop			; (mov r8, r8)
 80012c4:	fffff7ff 	.word	0xfffff7ff

080012c8 <TIM_OC1_SetConfig>:
  * @param  TIMx to select the TIM peripheral
  * @param  OC_Config The output configuration structure
  * @retval None
  */
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
 80012c8:	b530      	push	{r4, r5, lr}
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Disable the Channel 1: Reset the CC1E Bit */
  TIMx->CCER &= ~TIM_CCER_CC1E;
 80012ca:	6a03      	ldr	r3, [r0, #32]
 80012cc:	2201      	movs	r2, #1
 80012ce:	4393      	bics	r3, r2
 80012d0:	6203      	str	r3, [r0, #32]

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
 80012d2:	6a03      	ldr	r3, [r0, #32]
  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;
 80012d4:	6842      	ldr	r2, [r0, #4]

  /* Get the TIMx CCMR1 register value */
  tmpccmrx = TIMx->CCMR1;
 80012d6:	6984      	ldr	r4, [r0, #24]

  /* Reset the Output Compare Mode Bits */
  tmpccmrx &= ~TIM_CCMR1_OC1M;
  tmpccmrx &= ~TIM_CCMR1_CC1S;
 80012d8:	2573      	movs	r5, #115	; 0x73
 80012da:	43ac      	bics	r4, r5
  /* Select the Output Compare Mode */
  tmpccmrx |= OC_Config->OCMode;
 80012dc:	680d      	ldr	r5, [r1, #0]
 80012de:	432c      	orrs	r4, r5

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC1P;
 80012e0:	2502      	movs	r5, #2
 80012e2:	43ab      	bics	r3, r5
  /* Set the Output Compare Polarity */
  tmpccer |= OC_Config->OCPolarity;
 80012e4:	688d      	ldr	r5, [r1, #8]
 80012e6:	432b      	orrs	r3, r5

  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
 80012e8:	4d11      	ldr	r5, [pc, #68]	; (8001330 <TIM_OC1_SetConfig+0x68>)
 80012ea:	42a8      	cmp	r0, r5
 80012ec:	d005      	beq.n	80012fa <TIM_OC1_SetConfig+0x32>
 80012ee:	4d11      	ldr	r5, [pc, #68]	; (8001334 <TIM_OC1_SetConfig+0x6c>)
 80012f0:	42a8      	cmp	r0, r5
 80012f2:	d002      	beq.n	80012fa <TIM_OC1_SetConfig+0x32>
 80012f4:	4d10      	ldr	r5, [pc, #64]	; (8001338 <TIM_OC1_SetConfig+0x70>)
 80012f6:	42a8      	cmp	r0, r5
 80012f8:	d105      	bne.n	8001306 <TIM_OC1_SetConfig+0x3e>
  {
    /* Check parameters */
    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));

    /* Reset the Output N Polarity level */
    tmpccer &= ~TIM_CCER_CC1NP;
 80012fa:	2508      	movs	r5, #8
 80012fc:	43ab      	bics	r3, r5
    /* Set the Output N Polarity */
    tmpccer |= OC_Config->OCNPolarity;
 80012fe:	68cd      	ldr	r5, [r1, #12]
 8001300:	432b      	orrs	r3, r5
    /* Reset the Output N State */
    tmpccer &= ~TIM_CCER_CC1NE;
 8001302:	2504      	movs	r5, #4
 8001304:	43ab      	bics	r3, r5
  }

  if (IS_TIM_BREAK_INSTANCE(TIMx))
 8001306:	4d0a      	ldr	r5, [pc, #40]	; (8001330 <TIM_OC1_SetConfig+0x68>)
 8001308:	42a8      	cmp	r0, r5
 800130a:	d005      	beq.n	8001318 <TIM_OC1_SetConfig+0x50>
 800130c:	4d09      	ldr	r5, [pc, #36]	; (8001334 <TIM_OC1_SetConfig+0x6c>)
 800130e:	42a8      	cmp	r0, r5
 8001310:	d002      	beq.n	8001318 <TIM_OC1_SetConfig+0x50>
 8001312:	4d09      	ldr	r5, [pc, #36]	; (8001338 <TIM_OC1_SetConfig+0x70>)
 8001314:	42a8      	cmp	r0, r5
 8001316:	d105      	bne.n	8001324 <TIM_OC1_SetConfig+0x5c>
    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));

    /* Reset the Output Compare and Output Compare N IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS1;
    tmpcr2 &= ~TIM_CR2_OIS1N;
 8001318:	4d08      	ldr	r5, [pc, #32]	; (800133c <TIM_OC1_SetConfig+0x74>)
 800131a:	402a      	ands	r2, r5
    /* Set the Output Idle state */
    tmpcr2 |= OC_Config->OCIdleState;
 800131c:	694d      	ldr	r5, [r1, #20]
 800131e:	432a      	orrs	r2, r5
    /* Set the Output N Idle state */
    tmpcr2 |= OC_Config->OCNIdleState;
 8001320:	698d      	ldr	r5, [r1, #24]
 8001322:	432a      	orrs	r2, r5
  }

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;
 8001324:	6042      	str	r2, [r0, #4]

  /* Write to TIMx CCMR1 */
  TIMx->CCMR1 = tmpccmrx;
 8001326:	6184      	str	r4, [r0, #24]

  /* Set the Capture Compare Register value */
  TIMx->CCR1 = OC_Config->Pulse;
 8001328:	684a      	ldr	r2, [r1, #4]
 800132a:	6342      	str	r2, [r0, #52]	; 0x34

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
 800132c:	6203      	str	r3, [r0, #32]
}
 800132e:	bd30      	pop	{r4, r5, pc}
 8001330:	40012c00 	.word	0x40012c00
 8001334:	40014400 	.word	0x40014400
 8001338:	40014800 	.word	0x40014800
 800133c:	fffffcff 	.word	0xfffffcff

08001340 <TIM_OC3_SetConfig>:
  * @param  TIMx to select the TIM peripheral
  * @param  OC_Config The output configuration structure
  * @retval None
  */
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
 8001340:	b570      	push	{r4, r5, r6, lr}
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Disable the Channel 3: Reset the CC2E Bit */
  TIMx->CCER &= ~TIM_CCER_CC3E;
 8001342:	6a03      	ldr	r3, [r0, #32]
 8001344:	4a18      	ldr	r2, [pc, #96]	; (80013a8 <TIM_OC3_SetConfig+0x68>)
 8001346:	4013      	ands	r3, r2
 8001348:	6203      	str	r3, [r0, #32]

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
 800134a:	6a03      	ldr	r3, [r0, #32]
  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;
 800134c:	6844      	ldr	r4, [r0, #4]

  /* Get the TIMx CCMR2 register value */
  tmpccmrx = TIMx->CCMR2;
 800134e:	69c2      	ldr	r2, [r0, #28]

  /* Reset the Output Compare mode and Capture/Compare selection Bits */
  tmpccmrx &= ~TIM_CCMR2_OC3M;
  tmpccmrx &= ~TIM_CCMR2_CC3S;
 8001350:	2573      	movs	r5, #115	; 0x73
 8001352:	43aa      	bics	r2, r5
  /* Select the Output Compare Mode */
  tmpccmrx |= OC_Config->OCMode;
 8001354:	680e      	ldr	r6, [r1, #0]
 8001356:	4316      	orrs	r6, r2

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC3P;
 8001358:	4a14      	ldr	r2, [pc, #80]	; (80013ac <TIM_OC3_SetConfig+0x6c>)
 800135a:	4013      	ands	r3, r2
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 8U);
 800135c:	688a      	ldr	r2, [r1, #8]
 800135e:	0212      	lsls	r2, r2, #8
 8001360:	4313      	orrs	r3, r2

  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
 8001362:	4a13      	ldr	r2, [pc, #76]	; (80013b0 <TIM_OC3_SetConfig+0x70>)
 8001364:	4290      	cmp	r0, r2
 8001366:	d016      	beq.n	8001396 <TIM_OC3_SetConfig+0x56>
    tmpccer |= (OC_Config->OCNPolarity << 8U);
    /* Reset the Output N State */
    tmpccer &= ~TIM_CCER_CC3NE;
  }

  if (IS_TIM_BREAK_INSTANCE(TIMx))
 8001368:	4a11      	ldr	r2, [pc, #68]	; (80013b0 <TIM_OC3_SetConfig+0x70>)
 800136a:	4290      	cmp	r0, r2
 800136c:	d005      	beq.n	800137a <TIM_OC3_SetConfig+0x3a>
 800136e:	4a11      	ldr	r2, [pc, #68]	; (80013b4 <TIM_OC3_SetConfig+0x74>)
 8001370:	4290      	cmp	r0, r2
 8001372:	d002      	beq.n	800137a <TIM_OC3_SetConfig+0x3a>
 8001374:	4a10      	ldr	r2, [pc, #64]	; (80013b8 <TIM_OC3_SetConfig+0x78>)
 8001376:	4290      	cmp	r0, r2
 8001378:	d107      	bne.n	800138a <TIM_OC3_SetConfig+0x4a>
    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));

    /* Reset the Output Compare and Output Compare N IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS3;
    tmpcr2 &= ~TIM_CR2_OIS3N;
 800137a:	4a10      	ldr	r2, [pc, #64]	; (80013bc <TIM_OC3_SetConfig+0x7c>)
 800137c:	4022      	ands	r2, r4
    /* Set the Output Idle state */
    tmpcr2 |= (OC_Config->OCIdleState << 4U);
 800137e:	694c      	ldr	r4, [r1, #20]
 8001380:	0124      	lsls	r4, r4, #4
 8001382:	4314      	orrs	r4, r2
    /* Set the Output N Idle state */
    tmpcr2 |= (OC_Config->OCNIdleState << 4U);
 8001384:	698a      	ldr	r2, [r1, #24]
 8001386:	0115      	lsls	r5, r2, #4
 8001388:	432c      	orrs	r4, r5
  }

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;
 800138a:	6044      	str	r4, [r0, #4]

  /* Write to TIMx CCMR2 */
  TIMx->CCMR2 = tmpccmrx;
 800138c:	61c6      	str	r6, [r0, #28]

  /* Set the Capture Compare Register value */
  TIMx->CCR3 = OC_Config->Pulse;
 800138e:	684a      	ldr	r2, [r1, #4]
 8001390:	63c2      	str	r2, [r0, #60]	; 0x3c

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
 8001392:	6203      	str	r3, [r0, #32]
}
 8001394:	bd70      	pop	{r4, r5, r6, pc}
    tmpccer &= ~TIM_CCER_CC3NP;
 8001396:	4a0a      	ldr	r2, [pc, #40]	; (80013c0 <TIM_OC3_SetConfig+0x80>)
 8001398:	401a      	ands	r2, r3
    tmpccer |= (OC_Config->OCNPolarity << 8U);
 800139a:	68cb      	ldr	r3, [r1, #12]
 800139c:	021b      	lsls	r3, r3, #8
 800139e:	4313      	orrs	r3, r2
    tmpccer &= ~TIM_CCER_CC3NE;
 80013a0:	4a08      	ldr	r2, [pc, #32]	; (80013c4 <TIM_OC3_SetConfig+0x84>)
 80013a2:	4013      	ands	r3, r2
 80013a4:	e7e0      	b.n	8001368 <TIM_OC3_SetConfig+0x28>
 80013a6:	46c0      	nop			; (mov r8, r8)
 80013a8:	fffffeff 	.word	0xfffffeff
 80013ac:	fffffdff 	.word	0xfffffdff
 80013b0:	40012c00 	.word	0x40012c00
 80013b4:	40014400 	.word	0x40014400
 80013b8:	40014800 	.word	0x40014800
 80013bc:	ffffcfff 	.word	0xffffcfff
 80013c0:	fffff7ff 	.word	0xfffff7ff
 80013c4:	fffffbff 	.word	0xfffffbff

080013c8 <TIM_OC4_SetConfig>:
  * @param  TIMx to select the TIM peripheral
  * @param  OC_Config The output configuration structure
  * @retval None
  */
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
{
 80013c8:	b530      	push	{r4, r5, lr}
  uint32_t tmpccmrx;
  uint32_t tmpccer;
  uint32_t tmpcr2;

  /* Disable the Channel 4: Reset the CC4E Bit */
  TIMx->CCER &= ~TIM_CCER_CC4E;
 80013ca:	6a03      	ldr	r3, [r0, #32]
 80013cc:	4a11      	ldr	r2, [pc, #68]	; (8001414 <TIM_OC4_SetConfig+0x4c>)
 80013ce:	4013      	ands	r3, r2
 80013d0:	6203      	str	r3, [r0, #32]

  /* Get the TIMx CCER register value */
  tmpccer = TIMx->CCER;
 80013d2:	6a03      	ldr	r3, [r0, #32]
  /* Get the TIMx CR2 register value */
  tmpcr2 =  TIMx->CR2;
 80013d4:	6845      	ldr	r5, [r0, #4]

  /* Get the TIMx CCMR2 register value */
  tmpccmrx = TIMx->CCMR2;
 80013d6:	69c2      	ldr	r2, [r0, #28]

  /* Reset the Output Compare mode and Capture/Compare selection Bits */
  tmpccmrx &= ~TIM_CCMR2_OC4M;
  tmpccmrx &= ~TIM_CCMR2_CC4S;
 80013d8:	4c0f      	ldr	r4, [pc, #60]	; (8001418 <TIM_OC4_SetConfig+0x50>)
 80013da:	4022      	ands	r2, r4

  /* Select the Output Compare Mode */
  tmpccmrx |= (OC_Config->OCMode << 8U);
 80013dc:	680c      	ldr	r4, [r1, #0]
 80013de:	0224      	lsls	r4, r4, #8
 80013e0:	4322      	orrs	r2, r4

  /* Reset the Output Polarity level */
  tmpccer &= ~TIM_CCER_CC4P;
 80013e2:	4c0e      	ldr	r4, [pc, #56]	; (800141c <TIM_OC4_SetConfig+0x54>)
 80013e4:	401c      	ands	r4, r3
  /* Set the Output Compare Polarity */
  tmpccer |= (OC_Config->OCPolarity << 12U);
 80013e6:	688b      	ldr	r3, [r1, #8]
 80013e8:	031b      	lsls	r3, r3, #12
 80013ea:	4323      	orrs	r3, r4

  if (IS_TIM_BREAK_INSTANCE(TIMx))
 80013ec:	4c0c      	ldr	r4, [pc, #48]	; (8001420 <TIM_OC4_SetConfig+0x58>)
 80013ee:	42a0      	cmp	r0, r4
 80013f0:	d005      	beq.n	80013fe <TIM_OC4_SetConfig+0x36>
 80013f2:	4c0c      	ldr	r4, [pc, #48]	; (8001424 <TIM_OC4_SetConfig+0x5c>)
 80013f4:	42a0      	cmp	r0, r4
 80013f6:	d002      	beq.n	80013fe <TIM_OC4_SetConfig+0x36>
 80013f8:	4c0b      	ldr	r4, [pc, #44]	; (8001428 <TIM_OC4_SetConfig+0x60>)
 80013fa:	42a0      	cmp	r0, r4
 80013fc:	d104      	bne.n	8001408 <TIM_OC4_SetConfig+0x40>
  {
    /* Check parameters */
    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));

    /* Reset the Output Compare IDLE State */
    tmpcr2 &= ~TIM_CR2_OIS4;
 80013fe:	4c0b      	ldr	r4, [pc, #44]	; (800142c <TIM_OC4_SetConfig+0x64>)
 8001400:	4025      	ands	r5, r4

    /* Set the Output Idle state */
    tmpcr2 |= (OC_Config->OCIdleState << 6U);
 8001402:	694c      	ldr	r4, [r1, #20]
 8001404:	01a4      	lsls	r4, r4, #6
 8001406:	4325      	orrs	r5, r4
  }

  /* Write to TIMx CR2 */
  TIMx->CR2 = tmpcr2;
 8001408:	6045      	str	r5, [r0, #4]

  /* Write to TIMx CCMR2 */
  TIMx->CCMR2 = tmpccmrx;
 800140a:	61c2      	str	r2, [r0, #28]

  /* Set the Capture Compare Register value */
  TIMx->CCR4 = OC_Config->Pulse;
 800140c:	684a      	ldr	r2, [r1, #4]
 800140e:	6402      	str	r2, [r0, #64]	; 0x40

  /* Write to TIMx CCER */
  TIMx->CCER = tmpccer;
 8001410:	6203      	str	r3, [r0, #32]
}
 8001412:	bd30      	pop	{r4, r5, pc}
 8001414:	ffffefff 	.word	0xffffefff
 8001418:	ffff8cff 	.word	0xffff8cff
 800141c:	ffffdfff 	.word	0xffffdfff
 8001420:	40012c00 	.word	0x40012c00
 8001424:	40014400 	.word	0x40014400
 8001428:	40014800 	.word	0x40014800
 800142c:	ffffbfff 	.word	0xffffbfff

08001430 <TIM_TI1_ConfigInputStage>:
  * @param  TIM_ICFilter Specifies the Input Capture Filter.
  *          This parameter must be a value between 0x00 and 0x0F.
  * @retval None
  */
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
 8001430:	b530      	push	{r4, r5, lr}
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 1: Reset the CC1E Bit */
  tmpccer = TIMx->CCER;
 8001432:	6a03      	ldr	r3, [r0, #32]
  TIMx->CCER &= ~TIM_CCER_CC1E;
 8001434:	6a04      	ldr	r4, [r0, #32]
 8001436:	2501      	movs	r5, #1
 8001438:	43ac      	bics	r4, r5
 800143a:	6204      	str	r4, [r0, #32]
  tmpccmr1 = TIMx->CCMR1;
 800143c:	6984      	ldr	r4, [r0, #24]

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC1F;
 800143e:	35ef      	adds	r5, #239	; 0xef
 8001440:	43ac      	bics	r4, r5
  tmpccmr1 |= (TIM_ICFilter << 4U);
 8001442:	0112      	lsls	r2, r2, #4
 8001444:	4322      	orrs	r2, r4

  /* Select the Polarity and set the CC1E Bit */
  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
 8001446:	240a      	movs	r4, #10
 8001448:	43a3      	bics	r3, r4
  tmpccer |= TIM_ICPolarity;
 800144a:	430b      	orrs	r3, r1

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1;
 800144c:	6182      	str	r2, [r0, #24]
  TIMx->CCER = tmpccer;
 800144e:	6203      	str	r3, [r0, #32]
}
 8001450:	bd30      	pop	{r4, r5, pc}
	...

08001454 <TIM_TI2_ConfigInputStage>:
  * @param  TIM_ICFilter Specifies the Input Capture Filter.
  *          This parameter must be a value between 0x00 and 0x0F.
  * @retval None
  */
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
 8001454:	b530      	push	{r4, r5, lr}
  uint32_t tmpccmr1;
  uint32_t tmpccer;

  /* Disable the Channel 2: Reset the CC2E Bit */
  TIMx->CCER &= ~TIM_CCER_CC2E;
 8001456:	6a03      	ldr	r3, [r0, #32]
 8001458:	2410      	movs	r4, #16
 800145a:	43a3      	bics	r3, r4
 800145c:	6203      	str	r3, [r0, #32]
  tmpccmr1 = TIMx->CCMR1;
 800145e:	6984      	ldr	r4, [r0, #24]
  tmpccer = TIMx->CCER;
 8001460:	6a03      	ldr	r3, [r0, #32]

  /* Set the filter */
  tmpccmr1 &= ~TIM_CCMR1_IC2F;
 8001462:	4d05      	ldr	r5, [pc, #20]	; (8001478 <TIM_TI2_ConfigInputStage+0x24>)
 8001464:	402c      	ands	r4, r5
  tmpccmr1 |= (TIM_ICFilter << 12U);
 8001466:	0312      	lsls	r2, r2, #12
 8001468:	4322      	orrs	r2, r4

  /* Select the Polarity and set the CC2E Bit */
  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
 800146a:	24a0      	movs	r4, #160	; 0xa0
 800146c:	43a3      	bics	r3, r4
  tmpccer |= (TIM_ICPolarity << 4U);
 800146e:	0109      	lsls	r1, r1, #4
 8001470:	4319      	orrs	r1, r3

  /* Write to TIMx CCMR1 and CCER registers */
  TIMx->CCMR1 = tmpccmr1 ;
 8001472:	6182      	str	r2, [r0, #24]
  TIMx->CCER = tmpccer;
 8001474:	6201      	str	r1, [r0, #32]
}
 8001476:	bd30      	pop	{r4, r5, pc}
 8001478:	ffff0fff 	.word	0xffff0fff

0800147c <TIM_ITRx_SetConfig>:
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
  uint32_t tmpsmcr;

  /* Get the TIMx SMCR register value */
  tmpsmcr = TIMx->SMCR;
 800147c:	6883      	ldr	r3, [r0, #8]
  /* Reset the TS Bits */
  tmpsmcr &= ~TIM_SMCR_TS;
 800147e:	2270      	movs	r2, #112	; 0x70
 8001480:	4393      	bics	r3, r2
  /* Set the Input Trigger source and the slave mode*/
  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
 8001482:	430b      	orrs	r3, r1
 8001484:	2107      	movs	r1, #7
 8001486:	430b      	orrs	r3, r1
  /* Write to TIMx SMCR */
  TIMx->SMCR = tmpsmcr;
 8001488:	6083      	str	r3, [r0, #8]
}
 800148a:	4770      	bx	lr

0800148c <HAL_TIM_PWM_MspInit>:
}
 800148c:	4770      	bx	lr
	...

08001490 <TIM_Base_SetConfig>:
  tmpcr1 = TIMx->CR1;
 8001490:	6803      	ldr	r3, [r0, #0]
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 8001492:	4a1a      	ldr	r2, [pc, #104]	; (80014fc <TIM_Base_SetConfig+0x6c>)
 8001494:	4290      	cmp	r0, r2
 8001496:	d002      	beq.n	800149e <TIM_Base_SetConfig+0xe>
 8001498:	4a19      	ldr	r2, [pc, #100]	; (8001500 <TIM_Base_SetConfig+0x70>)
 800149a:	4290      	cmp	r0, r2
 800149c:	d103      	bne.n	80014a6 <TIM_Base_SetConfig+0x16>
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 800149e:	2270      	movs	r2, #112	; 0x70
 80014a0:	4393      	bics	r3, r2
    tmpcr1 |= Structure->CounterMode;
 80014a2:	684a      	ldr	r2, [r1, #4]
 80014a4:	4313      	orrs	r3, r2
  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 80014a6:	4a15      	ldr	r2, [pc, #84]	; (80014fc <TIM_Base_SetConfig+0x6c>)
 80014a8:	4290      	cmp	r0, r2
 80014aa:	d00b      	beq.n	80014c4 <TIM_Base_SetConfig+0x34>
 80014ac:	4a14      	ldr	r2, [pc, #80]	; (8001500 <TIM_Base_SetConfig+0x70>)
 80014ae:	4290      	cmp	r0, r2
 80014b0:	d008      	beq.n	80014c4 <TIM_Base_SetConfig+0x34>
 80014b2:	4a14      	ldr	r2, [pc, #80]	; (8001504 <TIM_Base_SetConfig+0x74>)
 80014b4:	4290      	cmp	r0, r2
 80014b6:	d005      	beq.n	80014c4 <TIM_Base_SetConfig+0x34>
 80014b8:	4a13      	ldr	r2, [pc, #76]	; (8001508 <TIM_Base_SetConfig+0x78>)
 80014ba:	4290      	cmp	r0, r2
 80014bc:	d002      	beq.n	80014c4 <TIM_Base_SetConfig+0x34>
 80014be:	4a13      	ldr	r2, [pc, #76]	; (800150c <TIM_Base_SetConfig+0x7c>)
 80014c0:	4290      	cmp	r0, r2
 80014c2:	d103      	bne.n	80014cc <TIM_Base_SetConfig+0x3c>
    tmpcr1 &= ~TIM_CR1_CKD;
 80014c4:	4a12      	ldr	r2, [pc, #72]	; (8001510 <TIM_Base_SetConfig+0x80>)
 80014c6:	4013      	ands	r3, r2
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 80014c8:	68ca      	ldr	r2, [r1, #12]
 80014ca:	4313      	orrs	r3, r2
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 80014cc:	2280      	movs	r2, #128	; 0x80
 80014ce:	4393      	bics	r3, r2
 80014d0:	694a      	ldr	r2, [r1, #20]
 80014d2:	4313      	orrs	r3, r2
  TIMx->CR1 = tmpcr1;
 80014d4:	6003      	str	r3, [r0, #0]
  TIMx->ARR = (uint32_t)Structure->Period ;
 80014d6:	688b      	ldr	r3, [r1, #8]
 80014d8:	62c3      	str	r3, [r0, #44]	; 0x2c
  TIMx->PSC = Structure->Prescaler;
 80014da:	680b      	ldr	r3, [r1, #0]
 80014dc:	6283      	str	r3, [r0, #40]	; 0x28
  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 80014de:	4b07      	ldr	r3, [pc, #28]	; (80014fc <TIM_Base_SetConfig+0x6c>)
 80014e0:	4298      	cmp	r0, r3
 80014e2:	d005      	beq.n	80014f0 <TIM_Base_SetConfig+0x60>
 80014e4:	4b08      	ldr	r3, [pc, #32]	; (8001508 <TIM_Base_SetConfig+0x78>)
 80014e6:	4298      	cmp	r0, r3
 80014e8:	d002      	beq.n	80014f0 <TIM_Base_SetConfig+0x60>
 80014ea:	4b08      	ldr	r3, [pc, #32]	; (800150c <TIM_Base_SetConfig+0x7c>)
 80014ec:	4298      	cmp	r0, r3
 80014ee:	d101      	bne.n	80014f4 <TIM_Base_SetConfig+0x64>
    TIMx->RCR = Structure->RepetitionCounter;
 80014f0:	690b      	ldr	r3, [r1, #16]
 80014f2:	6303      	str	r3, [r0, #48]	; 0x30
  TIMx->EGR = TIM_EGR_UG;
 80014f4:	2301      	movs	r3, #1
 80014f6:	6143      	str	r3, [r0, #20]
}
 80014f8:	4770      	bx	lr
 80014fa:	46c0      	nop			; (mov r8, r8)
 80014fc:	40012c00 	.word	0x40012c00
 8001500:	40000400 	.word	0x40000400
 8001504:	40002000 	.word	0x40002000
 8001508:	40014400 	.word	0x40014400
 800150c:	40014800 	.word	0x40014800
 8001510:	fffffcff 	.word	0xfffffcff

08001514 <HAL_TIM_Base_Init>:
{
 8001514:	b570      	push	{r4, r5, r6, lr}
 8001516:	1e04      	subs	r4, r0, #0
  if (htim == NULL)
 8001518:	d026      	beq.n	8001568 <HAL_TIM_Base_Init+0x54>
  if (htim->State == HAL_TIM_STATE_RESET)
 800151a:	233d      	movs	r3, #61	; 0x3d
 800151c:	5cc3      	ldrb	r3, [r0, r3]
 800151e:	2b00      	cmp	r3, #0
 8001520:	d01c      	beq.n	800155c <HAL_TIM_Base_Init+0x48>
  htim->State = HAL_TIM_STATE_BUSY;
 8001522:	253d      	movs	r5, #61	; 0x3d
 8001524:	2302      	movs	r3, #2
 8001526:	5563      	strb	r3, [r4, r5]
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 8001528:	0021      	movs	r1, r4
 800152a:	c901      	ldmia	r1!, {r0}
 800152c:	f7ff ffb0 	bl	8001490 <TIM_Base_SetConfig>
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
 8001530:	2301      	movs	r3, #1
 8001532:	2246      	movs	r2, #70	; 0x46
 8001534:	54a3      	strb	r3, [r4, r2]
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 8001536:	3a08      	subs	r2, #8
 8001538:	54a3      	strb	r3, [r4, r2]
 800153a:	3201      	adds	r2, #1
 800153c:	54a3      	strb	r3, [r4, r2]
 800153e:	3201      	adds	r2, #1
 8001540:	54a3      	strb	r3, [r4, r2]
 8001542:	3201      	adds	r2, #1
 8001544:	54a3      	strb	r3, [r4, r2]
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 8001546:	3201      	adds	r2, #1
 8001548:	54a3      	strb	r3, [r4, r2]
 800154a:	3201      	adds	r2, #1
 800154c:	54a3      	strb	r3, [r4, r2]
 800154e:	3201      	adds	r2, #1
 8001550:	54a3      	strb	r3, [r4, r2]
 8001552:	3201      	adds	r2, #1
 8001554:	54a3      	strb	r3, [r4, r2]
  htim->State = HAL_TIM_STATE_READY;
 8001556:	5563      	strb	r3, [r4, r5]
  return HAL_OK;
 8001558:	2000      	movs	r0, #0
}
 800155a:	bd70      	pop	{r4, r5, r6, pc}
    htim->Lock = HAL_UNLOCKED;
 800155c:	333c      	adds	r3, #60	; 0x3c
 800155e:	2200      	movs	r2, #0
 8001560:	54c2      	strb	r2, [r0, r3]
    HAL_TIM_Base_MspInit(htim);
 8001562:	f7ff f8ad 	bl	80006c0 <HAL_TIM_Base_MspInit>
 8001566:	e7dc      	b.n	8001522 <HAL_TIM_Base_Init+0xe>
    return HAL_ERROR;
 8001568:	2001      	movs	r0, #1
 800156a:	e7f6      	b.n	800155a <HAL_TIM_Base_Init+0x46>

0800156c <HAL_TIM_PWM_Init>:
{
 800156c:	b570      	push	{r4, r5, r6, lr}
 800156e:	1e04      	subs	r4, r0, #0
  if (htim == NULL)
 8001570:	d026      	beq.n	80015c0 <HAL_TIM_PWM_Init+0x54>
  if (htim->State == HAL_TIM_STATE_RESET)
 8001572:	233d      	movs	r3, #61	; 0x3d
 8001574:	5cc3      	ldrb	r3, [r0, r3]
 8001576:	2b00      	cmp	r3, #0
 8001578:	d01c      	beq.n	80015b4 <HAL_TIM_PWM_Init+0x48>
  htim->State = HAL_TIM_STATE_BUSY;
 800157a:	253d      	movs	r5, #61	; 0x3d
 800157c:	2302      	movs	r3, #2
 800157e:	5563      	strb	r3, [r4, r5]
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 8001580:	0021      	movs	r1, r4
 8001582:	c901      	ldmia	r1!, {r0}
 8001584:	f7ff ff84 	bl	8001490 <TIM_Base_SetConfig>
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
 8001588:	2301      	movs	r3, #1
 800158a:	2246      	movs	r2, #70	; 0x46
 800158c:	54a3      	strb	r3, [r4, r2]
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 800158e:	3a08      	subs	r2, #8
 8001590:	54a3      	strb	r3, [r4, r2]
 8001592:	3201      	adds	r2, #1
 8001594:	54a3      	strb	r3, [r4, r2]
 8001596:	3201      	adds	r2, #1
 8001598:	54a3      	strb	r3, [r4, r2]
 800159a:	3201      	adds	r2, #1
 800159c:	54a3      	strb	r3, [r4, r2]
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 800159e:	3201      	adds	r2, #1
 80015a0:	54a3      	strb	r3, [r4, r2]
 80015a2:	3201      	adds	r2, #1
 80015a4:	54a3      	strb	r3, [r4, r2]
 80015a6:	3201      	adds	r2, #1
 80015a8:	54a3      	strb	r3, [r4, r2]
 80015aa:	3201      	adds	r2, #1
 80015ac:	54a3      	strb	r3, [r4, r2]
  htim->State = HAL_TIM_STATE_READY;
 80015ae:	5563      	strb	r3, [r4, r5]
  return HAL_OK;
 80015b0:	2000      	movs	r0, #0
}
 80015b2:	bd70      	pop	{r4, r5, r6, pc}
    htim->Lock = HAL_UNLOCKED;
 80015b4:	333c      	adds	r3, #60	; 0x3c
 80015b6:	2200      	movs	r2, #0
 80015b8:	54c2      	strb	r2, [r0, r3]
    HAL_TIM_PWM_MspInit(htim);
 80015ba:	f7ff ff67 	bl	800148c <HAL_TIM_PWM_MspInit>
 80015be:	e7dc      	b.n	800157a <HAL_TIM_PWM_Init+0xe>
    return HAL_ERROR;
 80015c0:	2001      	movs	r0, #1
 80015c2:	e7f6      	b.n	80015b2 <HAL_TIM_PWM_Init+0x46>

080015c4 <TIM_OC2_SetConfig>:
{
 80015c4:	b530      	push	{r4, r5, lr}
  TIMx->CCER &= ~TIM_CCER_CC2E;
 80015c6:	6a03      	ldr	r3, [r0, #32]
 80015c8:	2210      	movs	r2, #16
 80015ca:	4393      	bics	r3, r2
 80015cc:	6203      	str	r3, [r0, #32]
  tmpccer = TIMx->CCER;
 80015ce:	6a03      	ldr	r3, [r0, #32]
  tmpcr2 =  TIMx->CR2;
 80015d0:	6845      	ldr	r5, [r0, #4]
  tmpccmrx = TIMx->CCMR1;
 80015d2:	6984      	ldr	r4, [r0, #24]
  tmpccmrx &= ~TIM_CCMR1_CC2S;
 80015d4:	4a16      	ldr	r2, [pc, #88]	; (8001630 <TIM_OC2_SetConfig+0x6c>)
 80015d6:	4014      	ands	r4, r2
  tmpccmrx |= (OC_Config->OCMode << 8U);
 80015d8:	680a      	ldr	r2, [r1, #0]
 80015da:	0212      	lsls	r2, r2, #8
 80015dc:	4314      	orrs	r4, r2
  tmpccer &= ~TIM_CCER_CC2P;
 80015de:	2220      	movs	r2, #32
 80015e0:	4393      	bics	r3, r2
  tmpccer |= (OC_Config->OCPolarity << 4U);
 80015e2:	688a      	ldr	r2, [r1, #8]
 80015e4:	0112      	lsls	r2, r2, #4
 80015e6:	4313      	orrs	r3, r2
  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
 80015e8:	4a12      	ldr	r2, [pc, #72]	; (8001634 <TIM_OC2_SetConfig+0x70>)
 80015ea:	4290      	cmp	r0, r2
 80015ec:	d016      	beq.n	800161c <TIM_OC2_SetConfig+0x58>
  if (IS_TIM_BREAK_INSTANCE(TIMx))
 80015ee:	4a11      	ldr	r2, [pc, #68]	; (8001634 <TIM_OC2_SetConfig+0x70>)
 80015f0:	4290      	cmp	r0, r2
 80015f2:	d005      	beq.n	8001600 <TIM_OC2_SetConfig+0x3c>
 80015f4:	4a10      	ldr	r2, [pc, #64]	; (8001638 <TIM_OC2_SetConfig+0x74>)
 80015f6:	4290      	cmp	r0, r2
 80015f8:	d002      	beq.n	8001600 <TIM_OC2_SetConfig+0x3c>
 80015fa:	4a10      	ldr	r2, [pc, #64]	; (800163c <TIM_OC2_SetConfig+0x78>)
 80015fc:	4290      	cmp	r0, r2
 80015fe:	d107      	bne.n	8001610 <TIM_OC2_SetConfig+0x4c>
    tmpcr2 &= ~TIM_CR2_OIS2N;
 8001600:	4a0f      	ldr	r2, [pc, #60]	; (8001640 <TIM_OC2_SetConfig+0x7c>)
 8001602:	402a      	ands	r2, r5
    tmpcr2 |= (OC_Config->OCIdleState << 2U);
 8001604:	694d      	ldr	r5, [r1, #20]
 8001606:	00ad      	lsls	r5, r5, #2
 8001608:	4315      	orrs	r5, r2
    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
 800160a:	698a      	ldr	r2, [r1, #24]
 800160c:	0092      	lsls	r2, r2, #2
 800160e:	4315      	orrs	r5, r2
  TIMx->CR2 = tmpcr2;
 8001610:	6045      	str	r5, [r0, #4]
  TIMx->CCMR1 = tmpccmrx;
 8001612:	6184      	str	r4, [r0, #24]
  TIMx->CCR2 = OC_Config->Pulse;
 8001614:	684a      	ldr	r2, [r1, #4]
 8001616:	6382      	str	r2, [r0, #56]	; 0x38
  TIMx->CCER = tmpccer;
 8001618:	6203      	str	r3, [r0, #32]
}
 800161a:	bd30      	pop	{r4, r5, pc}
    tmpccer &= ~TIM_CCER_CC2NP;
 800161c:	2280      	movs	r2, #128	; 0x80
 800161e:	4393      	bics	r3, r2
 8001620:	001a      	movs	r2, r3
    tmpccer |= (OC_Config->OCNPolarity << 4U);
 8001622:	68cb      	ldr	r3, [r1, #12]
 8001624:	011b      	lsls	r3, r3, #4
 8001626:	4313      	orrs	r3, r2
    tmpccer &= ~TIM_CCER_CC2NE;
 8001628:	2240      	movs	r2, #64	; 0x40
 800162a:	4393      	bics	r3, r2
 800162c:	e7df      	b.n	80015ee <TIM_OC2_SetConfig+0x2a>
 800162e:	46c0      	nop			; (mov r8, r8)
 8001630:	ffff8cff 	.word	0xffff8cff
 8001634:	40012c00 	.word	0x40012c00
 8001638:	40014400 	.word	0x40014400
 800163c:	40014800 	.word	0x40014800
 8001640:	fffff3ff 	.word	0xfffff3ff

08001644 <HAL_TIM_PWM_ConfigChannel>:
{
 8001644:	b570      	push	{r4, r5, r6, lr}
 8001646:	0004      	movs	r4, r0
 8001648:	000d      	movs	r5, r1
  __HAL_LOCK(htim);
 800164a:	233c      	movs	r3, #60	; 0x3c
 800164c:	5cc3      	ldrb	r3, [r0, r3]
 800164e:	2b01      	cmp	r3, #1
 8001650:	d100      	bne.n	8001654 <HAL_TIM_PWM_ConfigChannel+0x10>
 8001652:	e06a      	b.n	800172a <HAL_TIM_PWM_ConfigChannel+0xe6>
 8001654:	233c      	movs	r3, #60	; 0x3c
 8001656:	2101      	movs	r1, #1
 8001658:	54c1      	strb	r1, [r0, r3]
  switch (Channel)
 800165a:	2a08      	cmp	r2, #8
 800165c:	d050      	beq.n	8001700 <HAL_TIM_PWM_ConfigChannel+0xbc>
 800165e:	d81c      	bhi.n	800169a <HAL_TIM_PWM_ConfigChannel+0x56>
 8001660:	2a00      	cmp	r2, #0
 8001662:	d038      	beq.n	80016d6 <HAL_TIM_PWM_ConfigChannel+0x92>
 8001664:	2a04      	cmp	r2, #4
 8001666:	d116      	bne.n	8001696 <HAL_TIM_PWM_ConfigChannel+0x52>
      TIM_OC2_SetConfig(htim->Instance, sConfig);
 8001668:	0029      	movs	r1, r5
 800166a:	6800      	ldr	r0, [r0, #0]
 800166c:	f7ff ffaa 	bl	80015c4 <TIM_OC2_SetConfig>
      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
 8001670:	6822      	ldr	r2, [r4, #0]
 8001672:	6991      	ldr	r1, [r2, #24]
 8001674:	2380      	movs	r3, #128	; 0x80
 8001676:	011b      	lsls	r3, r3, #4
 8001678:	430b      	orrs	r3, r1
 800167a:	6193      	str	r3, [r2, #24]
      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
 800167c:	6822      	ldr	r2, [r4, #0]
 800167e:	6993      	ldr	r3, [r2, #24]
 8001680:	492b      	ldr	r1, [pc, #172]	; (8001730 <HAL_TIM_PWM_ConfigChannel+0xec>)
 8001682:	400b      	ands	r3, r1
 8001684:	6193      	str	r3, [r2, #24]
      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
 8001686:	6821      	ldr	r1, [r4, #0]
 8001688:	698b      	ldr	r3, [r1, #24]
 800168a:	692a      	ldr	r2, [r5, #16]
 800168c:	0212      	lsls	r2, r2, #8
 800168e:	4313      	orrs	r3, r2
 8001690:	618b      	str	r3, [r1, #24]
  HAL_StatusTypeDef status = HAL_OK;
 8001692:	2000      	movs	r0, #0
      break;
 8001694:	e01b      	b.n	80016ce <HAL_TIM_PWM_ConfigChannel+0x8a>
  switch (Channel)
 8001696:	0008      	movs	r0, r1
 8001698:	e019      	b.n	80016ce <HAL_TIM_PWM_ConfigChannel+0x8a>
 800169a:	2a0c      	cmp	r2, #12
 800169c:	d116      	bne.n	80016cc <HAL_TIM_PWM_ConfigChannel+0x88>
      TIM_OC4_SetConfig(htim->Instance, sConfig);
 800169e:	0029      	movs	r1, r5
 80016a0:	6800      	ldr	r0, [r0, #0]
 80016a2:	f7ff fe91 	bl	80013c8 <TIM_OC4_SetConfig>
      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
 80016a6:	6822      	ldr	r2, [r4, #0]
 80016a8:	69d1      	ldr	r1, [r2, #28]
 80016aa:	2380      	movs	r3, #128	; 0x80
 80016ac:	011b      	lsls	r3, r3, #4
 80016ae:	430b      	orrs	r3, r1
 80016b0:	61d3      	str	r3, [r2, #28]
      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
 80016b2:	6822      	ldr	r2, [r4, #0]
 80016b4:	69d3      	ldr	r3, [r2, #28]
 80016b6:	491e      	ldr	r1, [pc, #120]	; (8001730 <HAL_TIM_PWM_ConfigChannel+0xec>)
 80016b8:	400b      	ands	r3, r1
 80016ba:	61d3      	str	r3, [r2, #28]
      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
 80016bc:	6821      	ldr	r1, [r4, #0]
 80016be:	69cb      	ldr	r3, [r1, #28]
 80016c0:	692a      	ldr	r2, [r5, #16]
 80016c2:	0212      	lsls	r2, r2, #8
 80016c4:	4313      	orrs	r3, r2
 80016c6:	61cb      	str	r3, [r1, #28]
  HAL_StatusTypeDef status = HAL_OK;
 80016c8:	2000      	movs	r0, #0
      break;
 80016ca:	e000      	b.n	80016ce <HAL_TIM_PWM_ConfigChannel+0x8a>
  switch (Channel)
 80016cc:	2001      	movs	r0, #1
  __HAL_UNLOCK(htim);
 80016ce:	233c      	movs	r3, #60	; 0x3c
 80016d0:	2200      	movs	r2, #0
 80016d2:	54e2      	strb	r2, [r4, r3]
}
 80016d4:	bd70      	pop	{r4, r5, r6, pc}
      TIM_OC1_SetConfig(htim->Instance, sConfig);
 80016d6:	0029      	movs	r1, r5
 80016d8:	6800      	ldr	r0, [r0, #0]
 80016da:	f7ff fdf5 	bl	80012c8 <TIM_OC1_SetConfig>
      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
 80016de:	6822      	ldr	r2, [r4, #0]
 80016e0:	6993      	ldr	r3, [r2, #24]
 80016e2:	2108      	movs	r1, #8
 80016e4:	430b      	orrs	r3, r1
 80016e6:	6193      	str	r3, [r2, #24]
      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
 80016e8:	6822      	ldr	r2, [r4, #0]
 80016ea:	6993      	ldr	r3, [r2, #24]
 80016ec:	3904      	subs	r1, #4
 80016ee:	438b      	bics	r3, r1
 80016f0:	6193      	str	r3, [r2, #24]
      htim->Instance->CCMR1 |= sConfig->OCFastMode;
 80016f2:	6822      	ldr	r2, [r4, #0]
 80016f4:	6993      	ldr	r3, [r2, #24]
 80016f6:	6929      	ldr	r1, [r5, #16]
 80016f8:	430b      	orrs	r3, r1
 80016fa:	6193      	str	r3, [r2, #24]
  HAL_StatusTypeDef status = HAL_OK;
 80016fc:	2000      	movs	r0, #0
      break;
 80016fe:	e7e6      	b.n	80016ce <HAL_TIM_PWM_ConfigChannel+0x8a>
      TIM_OC3_SetConfig(htim->Instance, sConfig);
 8001700:	0029      	movs	r1, r5
 8001702:	6800      	ldr	r0, [r0, #0]
 8001704:	f7ff fe1c 	bl	8001340 <TIM_OC3_SetConfig>
      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
 8001708:	6822      	ldr	r2, [r4, #0]
 800170a:	69d3      	ldr	r3, [r2, #28]
 800170c:	2108      	movs	r1, #8
 800170e:	430b      	orrs	r3, r1
 8001710:	61d3      	str	r3, [r2, #28]
      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
 8001712:	6822      	ldr	r2, [r4, #0]
 8001714:	69d3      	ldr	r3, [r2, #28]
 8001716:	3904      	subs	r1, #4
 8001718:	438b      	bics	r3, r1
 800171a:	61d3      	str	r3, [r2, #28]
      htim->Instance->CCMR2 |= sConfig->OCFastMode;
 800171c:	6822      	ldr	r2, [r4, #0]
 800171e:	69d3      	ldr	r3, [r2, #28]
 8001720:	6929      	ldr	r1, [r5, #16]
 8001722:	430b      	orrs	r3, r1
 8001724:	61d3      	str	r3, [r2, #28]
  HAL_StatusTypeDef status = HAL_OK;
 8001726:	2000      	movs	r0, #0
      break;
 8001728:	e7d1      	b.n	80016ce <HAL_TIM_PWM_ConfigChannel+0x8a>
  __HAL_LOCK(htim);
 800172a:	2002      	movs	r0, #2
 800172c:	e7d2      	b.n	80016d4 <HAL_TIM_PWM_ConfigChannel+0x90>
 800172e:	46c0      	nop			; (mov r8, r8)
 8001730:	fffffbff 	.word	0xfffffbff

08001734 <TIM_ETR_SetConfig>:
  *          This parameter must be a value between 0x00 and 0x0F
  * @retval None
  */
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
 8001734:	b530      	push	{r4, r5, lr}
  uint32_t tmpsmcr;

  tmpsmcr = TIMx->SMCR;
 8001736:	6884      	ldr	r4, [r0, #8]

  /* Reset the ETR Bits */
  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
 8001738:	4d03      	ldr	r5, [pc, #12]	; (8001748 <TIM_ETR_SetConfig+0x14>)
 800173a:	402c      	ands	r4, r5

  /* Set the Prescaler, the Filter value and the Polarity */
  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
 800173c:	021b      	lsls	r3, r3, #8
 800173e:	4313      	orrs	r3, r2
 8001740:	430b      	orrs	r3, r1
 8001742:	4323      	orrs	r3, r4

  /* Write to TIMx SMCR */
  TIMx->SMCR = tmpsmcr;
 8001744:	6083      	str	r3, [r0, #8]
}
 8001746:	bd30      	pop	{r4, r5, pc}
 8001748:	ffff00ff 	.word	0xffff00ff

0800174c <HAL_TIM_ConfigClockSource>:
{
 800174c:	b510      	push	{r4, lr}
 800174e:	0004      	movs	r4, r0
  __HAL_LOCK(htim);
 8001750:	233c      	movs	r3, #60	; 0x3c
 8001752:	5cc3      	ldrb	r3, [r0, r3]
 8001754:	2b01      	cmp	r3, #1
 8001756:	d100      	bne.n	800175a <HAL_TIM_ConfigClockSource+0xe>
 8001758:	e078      	b.n	800184c <HAL_TIM_ConfigClockSource+0x100>
 800175a:	233c      	movs	r3, #60	; 0x3c
 800175c:	2201      	movs	r2, #1
 800175e:	54c2      	strb	r2, [r0, r3]
  htim->State = HAL_TIM_STATE_BUSY;
 8001760:	3301      	adds	r3, #1
 8001762:	3201      	adds	r2, #1
 8001764:	54c2      	strb	r2, [r0, r3]
  tmpsmcr = htim->Instance->SMCR;
 8001766:	6802      	ldr	r2, [r0, #0]
 8001768:	6893      	ldr	r3, [r2, #8]
  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
 800176a:	4839      	ldr	r0, [pc, #228]	; (8001850 <HAL_TIM_ConfigClockSource+0x104>)
 800176c:	4003      	ands	r3, r0
  htim->Instance->SMCR = tmpsmcr;
 800176e:	6093      	str	r3, [r2, #8]
  switch (sClockSourceConfig->ClockSource)
 8001770:	680b      	ldr	r3, [r1, #0]
 8001772:	2b60      	cmp	r3, #96	; 0x60
 8001774:	d050      	beq.n	8001818 <HAL_TIM_ConfigClockSource+0xcc>
 8001776:	d82a      	bhi.n	80017ce <HAL_TIM_ConfigClockSource+0x82>
 8001778:	2b40      	cmp	r3, #64	; 0x40
 800177a:	d058      	beq.n	800182e <HAL_TIM_ConfigClockSource+0xe2>
 800177c:	d90c      	bls.n	8001798 <HAL_TIM_ConfigClockSource+0x4c>
 800177e:	2b50      	cmp	r3, #80	; 0x50
 8001780:	d123      	bne.n	80017ca <HAL_TIM_ConfigClockSource+0x7e>
      TIM_TI1_ConfigInputStage(htim->Instance,
 8001782:	68ca      	ldr	r2, [r1, #12]
 8001784:	6849      	ldr	r1, [r1, #4]
 8001786:	6820      	ldr	r0, [r4, #0]
 8001788:	f7ff fe52 	bl	8001430 <TIM_TI1_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
 800178c:	2150      	movs	r1, #80	; 0x50
 800178e:	6820      	ldr	r0, [r4, #0]
 8001790:	f7ff fe74 	bl	800147c <TIM_ITRx_SetConfig>
  HAL_StatusTypeDef status = HAL_OK;
 8001794:	2000      	movs	r0, #0
      break;
 8001796:	e005      	b.n	80017a4 <HAL_TIM_ConfigClockSource+0x58>
  switch (sClockSourceConfig->ClockSource)
 8001798:	2b20      	cmp	r3, #32
 800179a:	d00e      	beq.n	80017ba <HAL_TIM_ConfigClockSource+0x6e>
 800179c:	d909      	bls.n	80017b2 <HAL_TIM_ConfigClockSource+0x66>
 800179e:	2b30      	cmp	r3, #48	; 0x30
 80017a0:	d00b      	beq.n	80017ba <HAL_TIM_ConfigClockSource+0x6e>
      status = HAL_ERROR;
 80017a2:	2001      	movs	r0, #1
  htim->State = HAL_TIM_STATE_READY;
 80017a4:	233d      	movs	r3, #61	; 0x3d
 80017a6:	2201      	movs	r2, #1
 80017a8:	54e2      	strb	r2, [r4, r3]
  __HAL_UNLOCK(htim);
 80017aa:	3b01      	subs	r3, #1
 80017ac:	2200      	movs	r2, #0
 80017ae:	54e2      	strb	r2, [r4, r3]
}
 80017b0:	bd10      	pop	{r4, pc}
  switch (sClockSourceConfig->ClockSource)
 80017b2:	2b00      	cmp	r3, #0
 80017b4:	d001      	beq.n	80017ba <HAL_TIM_ConfigClockSource+0x6e>
 80017b6:	2b10      	cmp	r3, #16
 80017b8:	d105      	bne.n	80017c6 <HAL_TIM_ConfigClockSource+0x7a>
      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
 80017ba:	0019      	movs	r1, r3
 80017bc:	6820      	ldr	r0, [r4, #0]
 80017be:	f7ff fe5d 	bl	800147c <TIM_ITRx_SetConfig>
  HAL_StatusTypeDef status = HAL_OK;
 80017c2:	2000      	movs	r0, #0
      break;
 80017c4:	e7ee      	b.n	80017a4 <HAL_TIM_ConfigClockSource+0x58>
      status = HAL_ERROR;
 80017c6:	2001      	movs	r0, #1
 80017c8:	e7ec      	b.n	80017a4 <HAL_TIM_ConfigClockSource+0x58>
 80017ca:	2001      	movs	r0, #1
 80017cc:	e7ea      	b.n	80017a4 <HAL_TIM_ConfigClockSource+0x58>
  switch (sClockSourceConfig->ClockSource)
 80017ce:	2280      	movs	r2, #128	; 0x80
 80017d0:	0152      	lsls	r2, r2, #5
 80017d2:	4293      	cmp	r3, r2
 80017d4:	d036      	beq.n	8001844 <HAL_TIM_ConfigClockSource+0xf8>
 80017d6:	2280      	movs	r2, #128	; 0x80
 80017d8:	0192      	lsls	r2, r2, #6
 80017da:	4293      	cmp	r3, r2
 80017dc:	d10d      	bne.n	80017fa <HAL_TIM_ConfigClockSource+0xae>
      TIM_ETR_SetConfig(htim->Instance,
 80017de:	68cb      	ldr	r3, [r1, #12]
 80017e0:	684a      	ldr	r2, [r1, #4]
 80017e2:	6889      	ldr	r1, [r1, #8]
 80017e4:	6820      	ldr	r0, [r4, #0]
 80017e6:	f7ff ffa5 	bl	8001734 <TIM_ETR_SetConfig>
      htim->Instance->SMCR |= TIM_SMCR_ECE;
 80017ea:	6822      	ldr	r2, [r4, #0]
 80017ec:	6891      	ldr	r1, [r2, #8]
 80017ee:	2380      	movs	r3, #128	; 0x80
 80017f0:	01db      	lsls	r3, r3, #7
 80017f2:	430b      	orrs	r3, r1
 80017f4:	6093      	str	r3, [r2, #8]
  HAL_StatusTypeDef status = HAL_OK;
 80017f6:	2000      	movs	r0, #0
      break;
 80017f8:	e7d4      	b.n	80017a4 <HAL_TIM_ConfigClockSource+0x58>
  switch (sClockSourceConfig->ClockSource)
 80017fa:	2b70      	cmp	r3, #112	; 0x70
 80017fc:	d124      	bne.n	8001848 <HAL_TIM_ConfigClockSource+0xfc>
      TIM_ETR_SetConfig(htim->Instance,
 80017fe:	68cb      	ldr	r3, [r1, #12]
 8001800:	684a      	ldr	r2, [r1, #4]
 8001802:	6889      	ldr	r1, [r1, #8]
 8001804:	6820      	ldr	r0, [r4, #0]
 8001806:	f7ff ff95 	bl	8001734 <TIM_ETR_SetConfig>
      tmpsmcr = htim->Instance->SMCR;
 800180a:	6822      	ldr	r2, [r4, #0]
 800180c:	6893      	ldr	r3, [r2, #8]
      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
 800180e:	2177      	movs	r1, #119	; 0x77
 8001810:	430b      	orrs	r3, r1
      htim->Instance->SMCR = tmpsmcr;
 8001812:	6093      	str	r3, [r2, #8]
  HAL_StatusTypeDef status = HAL_OK;
 8001814:	2000      	movs	r0, #0
      break;
 8001816:	e7c5      	b.n	80017a4 <HAL_TIM_ConfigClockSource+0x58>
      TIM_TI2_ConfigInputStage(htim->Instance,
 8001818:	68ca      	ldr	r2, [r1, #12]
 800181a:	6849      	ldr	r1, [r1, #4]
 800181c:	6820      	ldr	r0, [r4, #0]
 800181e:	f7ff fe19 	bl	8001454 <TIM_TI2_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
 8001822:	2160      	movs	r1, #96	; 0x60
 8001824:	6820      	ldr	r0, [r4, #0]
 8001826:	f7ff fe29 	bl	800147c <TIM_ITRx_SetConfig>
  HAL_StatusTypeDef status = HAL_OK;
 800182a:	2000      	movs	r0, #0
      break;
 800182c:	e7ba      	b.n	80017a4 <HAL_TIM_ConfigClockSource+0x58>
      TIM_TI1_ConfigInputStage(htim->Instance,
 800182e:	68ca      	ldr	r2, [r1, #12]
 8001830:	6849      	ldr	r1, [r1, #4]
 8001832:	6820      	ldr	r0, [r4, #0]
 8001834:	f7ff fdfc 	bl	8001430 <TIM_TI1_ConfigInputStage>
      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
 8001838:	2140      	movs	r1, #64	; 0x40
 800183a:	6820      	ldr	r0, [r4, #0]
 800183c:	f7ff fe1e 	bl	800147c <TIM_ITRx_SetConfig>
  HAL_StatusTypeDef status = HAL_OK;
 8001840:	2000      	movs	r0, #0
      break;
 8001842:	e7af      	b.n	80017a4 <HAL_TIM_ConfigClockSource+0x58>
  switch (sClockSourceConfig->ClockSource)
 8001844:	2000      	movs	r0, #0
 8001846:	e7ad      	b.n	80017a4 <HAL_TIM_ConfigClockSource+0x58>
      status = HAL_ERROR;
 8001848:	2001      	movs	r0, #1
 800184a:	e7ab      	b.n	80017a4 <HAL_TIM_ConfigClockSource+0x58>
  __HAL_LOCK(htim);
 800184c:	2002      	movs	r0, #2
 800184e:	e7af      	b.n	80017b0 <HAL_TIM_ConfigClockSource+0x64>
 8001850:	ffff0088 	.word	0xffff0088

08001854 <TIM_CCxChannelCmd>:
  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
  * @retval None
  */
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
 8001854:	b510      	push	{r4, lr}

  /* Check the parameters */
  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
  assert_param(IS_TIM_CHANNELS(Channel));

  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
 8001856:	231f      	movs	r3, #31
 8001858:	4019      	ands	r1, r3
 800185a:	2401      	movs	r4, #1
 800185c:	408c      	lsls	r4, r1

  /* Reset the CCxE Bit */
  TIMx->CCER &= ~tmp;
 800185e:	6a03      	ldr	r3, [r0, #32]
 8001860:	43a3      	bics	r3, r4
 8001862:	6203      	str	r3, [r0, #32]

  /* Set or reset the CCxE Bit */
  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
 8001864:	6a03      	ldr	r3, [r0, #32]
 8001866:	408a      	lsls	r2, r1
 8001868:	4313      	orrs	r3, r2
 800186a:	6203      	str	r3, [r0, #32]
}
 800186c:	bd10      	pop	{r4, pc}
	...

08001870 <HAL_TIM_PWM_Start>:
{
 8001870:	b510      	push	{r4, lr}
 8001872:	0004      	movs	r4, r0
  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
 8001874:	2900      	cmp	r1, #0
 8001876:	d12c      	bne.n	80018d2 <HAL_TIM_PWM_Start+0x62>
 8001878:	233e      	movs	r3, #62	; 0x3e
 800187a:	5cc3      	ldrb	r3, [r0, r3]
 800187c:	3b01      	subs	r3, #1
 800187e:	1e5a      	subs	r2, r3, #1
 8001880:	4193      	sbcs	r3, r2
 8001882:	b2db      	uxtb	r3, r3
 8001884:	2b00      	cmp	r3, #0
 8001886:	d158      	bne.n	800193a <HAL_TIM_PWM_Start+0xca>
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
 8001888:	2900      	cmp	r1, #0
 800188a:	d13b      	bne.n	8001904 <HAL_TIM_PWM_Start+0x94>
 800188c:	333e      	adds	r3, #62	; 0x3e
 800188e:	2202      	movs	r2, #2
 8001890:	54e2      	strb	r2, [r4, r3]
  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
 8001892:	2201      	movs	r2, #1
 8001894:	6820      	ldr	r0, [r4, #0]
 8001896:	f7ff ffdd 	bl	8001854 <TIM_CCxChannelCmd>
  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
 800189a:	6823      	ldr	r3, [r4, #0]
 800189c:	4a29      	ldr	r2, [pc, #164]	; (8001944 <HAL_TIM_PWM_Start+0xd4>)
 800189e:	4293      	cmp	r3, r2
 80018a0:	d005      	beq.n	80018ae <HAL_TIM_PWM_Start+0x3e>
 80018a2:	4a29      	ldr	r2, [pc, #164]	; (8001948 <HAL_TIM_PWM_Start+0xd8>)
 80018a4:	4293      	cmp	r3, r2
 80018a6:	d002      	beq.n	80018ae <HAL_TIM_PWM_Start+0x3e>
 80018a8:	4a28      	ldr	r2, [pc, #160]	; (800194c <HAL_TIM_PWM_Start+0xdc>)
 80018aa:	4293      	cmp	r3, r2
 80018ac:	d104      	bne.n	80018b8 <HAL_TIM_PWM_Start+0x48>
    __HAL_TIM_MOE_ENABLE(htim);
 80018ae:	6c59      	ldr	r1, [r3, #68]	; 0x44
 80018b0:	2280      	movs	r2, #128	; 0x80
 80018b2:	0212      	lsls	r2, r2, #8
 80018b4:	430a      	orrs	r2, r1
 80018b6:	645a      	str	r2, [r3, #68]	; 0x44
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 80018b8:	6823      	ldr	r3, [r4, #0]
 80018ba:	4a22      	ldr	r2, [pc, #136]	; (8001944 <HAL_TIM_PWM_Start+0xd4>)
 80018bc:	4293      	cmp	r3, r2
 80018be:	d031      	beq.n	8001924 <HAL_TIM_PWM_Start+0xb4>
 80018c0:	4a23      	ldr	r2, [pc, #140]	; (8001950 <HAL_TIM_PWM_Start+0xe0>)
 80018c2:	4293      	cmp	r3, r2
 80018c4:	d02e      	beq.n	8001924 <HAL_TIM_PWM_Start+0xb4>
    __HAL_TIM_ENABLE(htim);
 80018c6:	681a      	ldr	r2, [r3, #0]
 80018c8:	2101      	movs	r1, #1
 80018ca:	430a      	orrs	r2, r1
 80018cc:	601a      	str	r2, [r3, #0]
  return HAL_OK;
 80018ce:	2000      	movs	r0, #0
 80018d0:	e034      	b.n	800193c <HAL_TIM_PWM_Start+0xcc>
  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
 80018d2:	2904      	cmp	r1, #4
 80018d4:	d008      	beq.n	80018e8 <HAL_TIM_PWM_Start+0x78>
 80018d6:	2908      	cmp	r1, #8
 80018d8:	d00d      	beq.n	80018f6 <HAL_TIM_PWM_Start+0x86>
 80018da:	2341      	movs	r3, #65	; 0x41
 80018dc:	5cc3      	ldrb	r3, [r0, r3]
 80018de:	3b01      	subs	r3, #1
 80018e0:	1e5a      	subs	r2, r3, #1
 80018e2:	4193      	sbcs	r3, r2
 80018e4:	b2db      	uxtb	r3, r3
 80018e6:	e7cd      	b.n	8001884 <HAL_TIM_PWM_Start+0x14>
 80018e8:	233f      	movs	r3, #63	; 0x3f
 80018ea:	5cc3      	ldrb	r3, [r0, r3]
 80018ec:	3b01      	subs	r3, #1
 80018ee:	1e5a      	subs	r2, r3, #1
 80018f0:	4193      	sbcs	r3, r2
 80018f2:	b2db      	uxtb	r3, r3
 80018f4:	e7c6      	b.n	8001884 <HAL_TIM_PWM_Start+0x14>
 80018f6:	2340      	movs	r3, #64	; 0x40
 80018f8:	5cc3      	ldrb	r3, [r0, r3]
 80018fa:	3b01      	subs	r3, #1
 80018fc:	1e5a      	subs	r2, r3, #1
 80018fe:	4193      	sbcs	r3, r2
 8001900:	b2db      	uxtb	r3, r3
 8001902:	e7bf      	b.n	8001884 <HAL_TIM_PWM_Start+0x14>
  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
 8001904:	2904      	cmp	r1, #4
 8001906:	d005      	beq.n	8001914 <HAL_TIM_PWM_Start+0xa4>
 8001908:	2908      	cmp	r1, #8
 800190a:	d007      	beq.n	800191c <HAL_TIM_PWM_Start+0xac>
 800190c:	2341      	movs	r3, #65	; 0x41
 800190e:	2202      	movs	r2, #2
 8001910:	54e2      	strb	r2, [r4, r3]
 8001912:	e7be      	b.n	8001892 <HAL_TIM_PWM_Start+0x22>
 8001914:	233f      	movs	r3, #63	; 0x3f
 8001916:	2202      	movs	r2, #2
 8001918:	54e2      	strb	r2, [r4, r3]
 800191a:	e7ba      	b.n	8001892 <HAL_TIM_PWM_Start+0x22>
 800191c:	2340      	movs	r3, #64	; 0x40
 800191e:	2202      	movs	r2, #2
 8001920:	54e2      	strb	r2, [r4, r3]
 8001922:	e7b6      	b.n	8001892 <HAL_TIM_PWM_Start+0x22>
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 8001924:	6899      	ldr	r1, [r3, #8]
 8001926:	2207      	movs	r2, #7
 8001928:	400a      	ands	r2, r1
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800192a:	2a06      	cmp	r2, #6
 800192c:	d007      	beq.n	800193e <HAL_TIM_PWM_Start+0xce>
      __HAL_TIM_ENABLE(htim);
 800192e:	681a      	ldr	r2, [r3, #0]
 8001930:	2101      	movs	r1, #1
 8001932:	430a      	orrs	r2, r1
 8001934:	601a      	str	r2, [r3, #0]
  return HAL_OK;
 8001936:	2000      	movs	r0, #0
 8001938:	e000      	b.n	800193c <HAL_TIM_PWM_Start+0xcc>
    return HAL_ERROR;
 800193a:	2001      	movs	r0, #1
}
 800193c:	bd10      	pop	{r4, pc}
  return HAL_OK;
 800193e:	2000      	movs	r0, #0
 8001940:	e7fc      	b.n	800193c <HAL_TIM_PWM_Start+0xcc>
 8001942:	46c0      	nop			; (mov r8, r8)
 8001944:	40012c00 	.word	0x40012c00
 8001948:	40014400 	.word	0x40014400
 800194c:	40014800 	.word	0x40014800
 8001950:	40000400 	.word	0x40000400

08001954 <HAL_TIMEx_MasterConfigSynchronization>:
  *         mode.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
                                                        TIM_MasterConfigTypeDef *sMasterConfig)
{
 8001954:	b530      	push	{r4, r5, lr}
  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));

  /* Check input state */
  __HAL_LOCK(htim);
 8001956:	233c      	movs	r3, #60	; 0x3c
 8001958:	5cc3      	ldrb	r3, [r0, r3]
 800195a:	2b01      	cmp	r3, #1
 800195c:	d021      	beq.n	80019a2 <HAL_TIMEx_MasterConfigSynchronization+0x4e>
 800195e:	233c      	movs	r3, #60	; 0x3c
 8001960:	2201      	movs	r2, #1
 8001962:	54c2      	strb	r2, [r0, r3]

  /* Change the handler state */
  htim->State = HAL_TIM_STATE_BUSY;
 8001964:	3301      	adds	r3, #1
 8001966:	3201      	adds	r2, #1
 8001968:	54c2      	strb	r2, [r0, r3]

  /* Get the TIMx CR2 register value */
  tmpcr2 = htim->Instance->CR2;
 800196a:	6803      	ldr	r3, [r0, #0]
 800196c:	685a      	ldr	r2, [r3, #4]

  /* Get the TIMx SMCR register value */
  tmpsmcr = htim->Instance->SMCR;
 800196e:	689c      	ldr	r4, [r3, #8]

  /* Reset the MMS Bits */
  tmpcr2 &= ~TIM_CR2_MMS;
 8001970:	2570      	movs	r5, #112	; 0x70
 8001972:	43aa      	bics	r2, r5
  /* Select the TRGO source */
  tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
 8001974:	680d      	ldr	r5, [r1, #0]
 8001976:	432a      	orrs	r2, r5

  /* Update TIMx CR2 */
  htim->Instance->CR2 = tmpcr2;
 8001978:	605a      	str	r2, [r3, #4]

  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 800197a:	6803      	ldr	r3, [r0, #0]
 800197c:	4a0a      	ldr	r2, [pc, #40]	; (80019a8 <HAL_TIMEx_MasterConfigSynchronization+0x54>)
 800197e:	4293      	cmp	r3, r2
 8001980:	d002      	beq.n	8001988 <HAL_TIMEx_MasterConfigSynchronization+0x34>
 8001982:	4a0a      	ldr	r2, [pc, #40]	; (80019ac <HAL_TIMEx_MasterConfigSynchronization+0x58>)
 8001984:	4293      	cmp	r3, r2
 8001986:	d104      	bne.n	8001992 <HAL_TIMEx_MasterConfigSynchronization+0x3e>
  {
    /* Reset the MSM Bit */
    tmpsmcr &= ~TIM_SMCR_MSM;
 8001988:	2280      	movs	r2, #128	; 0x80
 800198a:	4394      	bics	r4, r2
    /* Set master mode */
    tmpsmcr |= sMasterConfig->MasterSlaveMode;
 800198c:	684a      	ldr	r2, [r1, #4]
 800198e:	4314      	orrs	r4, r2

    /* Update TIMx SMCR */
    htim->Instance->SMCR = tmpsmcr;
 8001990:	609c      	str	r4, [r3, #8]
  }

  /* Change the htim state */
  htim->State = HAL_TIM_STATE_READY;
 8001992:	233d      	movs	r3, #61	; 0x3d
 8001994:	2201      	movs	r2, #1
 8001996:	54c2      	strb	r2, [r0, r3]

  __HAL_UNLOCK(htim);
 8001998:	3b01      	subs	r3, #1
 800199a:	2200      	movs	r2, #0
 800199c:	54c2      	strb	r2, [r0, r3]

  return HAL_OK;
 800199e:	2000      	movs	r0, #0
}
 80019a0:	bd30      	pop	{r4, r5, pc}
  __HAL_LOCK(htim);
 80019a2:	2002      	movs	r0, #2
 80019a4:	e7fc      	b.n	80019a0 <HAL_TIMEx_MasterConfigSynchronization+0x4c>
 80019a6:	46c0      	nop			; (mov r8, r8)
 80019a8:	40012c00 	.word	0x40012c00
 80019ac:	40000400 	.word	0x40000400

080019b0 <HAL_TIMEx_ConfigBreakDeadTime>:
  *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
 80019b0:	b510      	push	{r4, lr}
  assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
  assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));

  /* Check input state */
  __HAL_LOCK(htim);
 80019b2:	233c      	movs	r3, #60	; 0x3c
 80019b4:	5cc3      	ldrb	r3, [r0, r3]
 80019b6:	2b01      	cmp	r3, #1
 80019b8:	d021      	beq.n	80019fe <HAL_TIMEx_ConfigBreakDeadTime+0x4e>
 80019ba:	223c      	movs	r2, #60	; 0x3c
 80019bc:	2301      	movs	r3, #1
 80019be:	5483      	strb	r3, [r0, r2]
  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
     the OSSI State, the dead time value and the Automatic Output Enable Bit */

  /* Set the BDTR bits */
  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
 80019c0:	4b10      	ldr	r3, [pc, #64]	; (8001a04 <HAL_TIMEx_ConfigBreakDeadTime+0x54>)
 80019c2:	68cc      	ldr	r4, [r1, #12]
 80019c4:	4023      	ands	r3, r4
 80019c6:	688c      	ldr	r4, [r1, #8]
 80019c8:	4323      	orrs	r3, r4
  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
 80019ca:	4c0f      	ldr	r4, [pc, #60]	; (8001a08 <HAL_TIMEx_ConfigBreakDeadTime+0x58>)
 80019cc:	4023      	ands	r3, r4
 80019ce:	684c      	ldr	r4, [r1, #4]
 80019d0:	4323      	orrs	r3, r4
  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
 80019d2:	4c0e      	ldr	r4, [pc, #56]	; (8001a0c <HAL_TIMEx_ConfigBreakDeadTime+0x5c>)
 80019d4:	4023      	ands	r3, r4
 80019d6:	680c      	ldr	r4, [r1, #0]
 80019d8:	4323      	orrs	r3, r4
  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
 80019da:	4c0d      	ldr	r4, [pc, #52]	; (8001a10 <HAL_TIMEx_ConfigBreakDeadTime+0x60>)
 80019dc:	4023      	ands	r3, r4
 80019de:	690c      	ldr	r4, [r1, #16]
 80019e0:	4323      	orrs	r3, r4
  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
 80019e2:	4c0c      	ldr	r4, [pc, #48]	; (8001a14 <HAL_TIMEx_ConfigBreakDeadTime+0x64>)
 80019e4:	4023      	ands	r3, r4
 80019e6:	694c      	ldr	r4, [r1, #20]
 80019e8:	4323      	orrs	r3, r4
  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
 80019ea:	4c0b      	ldr	r4, [pc, #44]	; (8001a18 <HAL_TIMEx_ConfigBreakDeadTime+0x68>)
 80019ec:	4023      	ands	r3, r4
 80019ee:	69c9      	ldr	r1, [r1, #28]
 80019f0:	430b      	orrs	r3, r1


  /* Set TIMx_BDTR */
  htim->Instance->BDTR = tmpbdtr;
 80019f2:	6801      	ldr	r1, [r0, #0]
 80019f4:	644b      	str	r3, [r1, #68]	; 0x44

  __HAL_UNLOCK(htim);
 80019f6:	2300      	movs	r3, #0
 80019f8:	5483      	strb	r3, [r0, r2]

  return HAL_OK;
 80019fa:	2000      	movs	r0, #0
}
 80019fc:	bd10      	pop	{r4, pc}
  __HAL_LOCK(htim);
 80019fe:	2002      	movs	r0, #2
 8001a00:	e7fc      	b.n	80019fc <HAL_TIMEx_ConfigBreakDeadTime+0x4c>
 8001a02:	46c0      	nop			; (mov r8, r8)
 8001a04:	fffffcff 	.word	0xfffffcff
 8001a08:	fffffbff 	.word	0xfffffbff
 8001a0c:	fffff7ff 	.word	0xfffff7ff
 8001a10:	ffffefff 	.word	0xffffefff
 8001a14:	ffffdfff 	.word	0xffffdfff
 8001a18:	ffffbfff 	.word	0xffffbfff

08001a1c <__libc_init_array>:
 8001a1c:	b570      	push	{r4, r5, r6, lr}
 8001a1e:	2600      	movs	r6, #0
 8001a20:	4d0c      	ldr	r5, [pc, #48]	; (8001a54 <__libc_init_array+0x38>)
 8001a22:	4c0d      	ldr	r4, [pc, #52]	; (8001a58 <__libc_init_array+0x3c>)
 8001a24:	1b64      	subs	r4, r4, r5
 8001a26:	10a4      	asrs	r4, r4, #2
 8001a28:	42a6      	cmp	r6, r4
 8001a2a:	d109      	bne.n	8001a40 <__libc_init_array+0x24>
 8001a2c:	2600      	movs	r6, #0
 8001a2e:	f000 f821 	bl	8001a74 <_init>
 8001a32:	4d0a      	ldr	r5, [pc, #40]	; (8001a5c <__libc_init_array+0x40>)
 8001a34:	4c0a      	ldr	r4, [pc, #40]	; (8001a60 <__libc_init_array+0x44>)
 8001a36:	1b64      	subs	r4, r4, r5
 8001a38:	10a4      	asrs	r4, r4, #2
 8001a3a:	42a6      	cmp	r6, r4
 8001a3c:	d105      	bne.n	8001a4a <__libc_init_array+0x2e>
 8001a3e:	bd70      	pop	{r4, r5, r6, pc}
 8001a40:	00b3      	lsls	r3, r6, #2
 8001a42:	58eb      	ldr	r3, [r5, r3]
 8001a44:	4798      	blx	r3
 8001a46:	3601      	adds	r6, #1
 8001a48:	e7ee      	b.n	8001a28 <__libc_init_array+0xc>
 8001a4a:	00b3      	lsls	r3, r6, #2
 8001a4c:	58eb      	ldr	r3, [r5, r3]
 8001a4e:	4798      	blx	r3
 8001a50:	3601      	adds	r6, #1
 8001a52:	e7f2      	b.n	8001a3a <__libc_init_array+0x1e>
 8001a54:	08001ac4 	.word	0x08001ac4
 8001a58:	08001ac4 	.word	0x08001ac4
 8001a5c:	08001ac4 	.word	0x08001ac4
 8001a60:	08001ac8 	.word	0x08001ac8

08001a64 <memset>:
 8001a64:	0003      	movs	r3, r0
 8001a66:	1882      	adds	r2, r0, r2
 8001a68:	4293      	cmp	r3, r2
 8001a6a:	d100      	bne.n	8001a6e <memset+0xa>
 8001a6c:	4770      	bx	lr
 8001a6e:	7019      	strb	r1, [r3, #0]
 8001a70:	3301      	adds	r3, #1
 8001a72:	e7f9      	b.n	8001a68 <memset+0x4>

08001a74 <_init>:
 8001a74:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8001a76:	46c0      	nop			; (mov r8, r8)
 8001a78:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8001a7a:	bc08      	pop	{r3}
 8001a7c:	469e      	mov	lr, r3
 8001a7e:	4770      	bx	lr

08001a80 <_fini>:
 8001a80:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8001a82:	46c0      	nop			; (mov r8, r8)
 8001a84:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8001a86:	bc08      	pop	{r3}
 8001a88:	469e      	mov	lr, r3
 8001a8a:	4770      	bx	lr